FINAL
Am28F020
2 Megabit (256 K x 8-Bit)
CMOS 12.0 Volt, Bulk Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
s
High performance
— Access times as fast as 70 ns
s
CMOS low power consumption
— 30 mA maximum active current
— 100 µA maximum standby current
— No data retention power consumption
s
Compatible with JEDEC-standard byte-wide
32-pin EPROM pinouts
— 32-pin PDIP
— 32-pin PLCC
— 32-pin TSOP
s
10,000 write/erase cycles minimum
s
Write and erase voltage 12.0 V
±5%
s
Latch-up protected to 100 mA from
–1 V to V
CC
+1 V
s
Flasherase Electrical Bulk Chip Erase
— One second typical chip erase time
s
Flashrite Programming
— 10 µs typical byte program time
— 4 s typical chip program time
s
Command register architecture for
microprocessor/microcontroller compatible
write interface
s
On-chip address and data latches
s
Advanced CMOS flash memory technology
— Low cost single transistor memory cell
s
Automatic write/erase pulse stop timer
GENERAL DESCRIPTION
The Am28F020 is a 2 Megabit Flash memory orga-
nized as 256 Kbytes of 8 bits each. AMD’s Flash mem-
ories offer the most cost-effective and reliable read/
write non-volatile random access memor y. The
Am28F020 is packaged in 32-pin PDIP, PLCC, and
TSOP versions. It is designed to be reprogrammed and
erased in-system or in standard EPROM programmers.
Th e Am 28F 020 i s eras ed w hen s h ip ped from
the factory.
The standard Am28F020 offers access times of as fast
as 70 ns, allowing high speed microprocessors to
operate without wait states. To eliminate bus conten-
tion, the device has separate chip enable (CE#) and
output enable (OE#) controls.
AMD’s Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
Am28F020 uses a command register to manage this
functionality, while maintaining a JEDEC-standard 32-
pin pinout. The command register allows for 100% TTL
level control inputs and fixed power supply levels during
erase and programming, while maintaining maximum
EPROM compatibility.
AMD’s Flash technology reliably stores memory con-
tents even after 10,000 erase and program cycles. The
AMD cell is designed to optimize the erase and pro-
gramming mechanisms. In addition, the combination of
advanced tunnel oxide processing and low internal
electric fields for erase and programming operations
produces reliable cycling. The Am28F020 uses a
12.0±5% V
PP
supply input to perform the Flasherase
and Flashrite functions.
The highest degree of latch-up protection is achieved
with AMD’s proprietary non-epi process. Latch-up pro-
tection is provided for stresses up to 100 mA on
address and data pins from –1 V to V
CC
+1 V.
The Am28F020 is byte programmable using 10 µs
programming pulses in accordance with AMD’s
Flashrite programming algorithm. The typical room
temperature programming time of the Am28F020 is
four seconds. The entire chip is bulk erased using 10
ms erase pulses according to AMD’s Flasherase
algorithm. Typical erasure at room temperature is
accomplished in less than one second. The windowed
package and the 15–20 minutes required for EPROM
erasure using ultraviolet light are eliminated.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine, which
controls the erase and programming circuitry. During
write cycles, the command register internally latches
Publication#
14727
Rev:
F
Amendment/+2
Issue Date:
January 1998
addresses and data needed for the programming and
erase operations. For system design simplification, the
Am28F020 is designed to support either WE# or CE#
controlled w rites. During a system write cycle,
addresses are latched on the falling edge of WE# or
CE#, whichever occurs last. Data is latched on the rising
edge of WE# or CE#, whichever occurs first. To simplify
discussion, the WE# pin is used as the write cycle
control pin throughout the rest of this data sheet. All
setup and hold times are with respect to the WE# signal.
AMD’s Flash technology combines years of EPROM
and EEPROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The
Am28F020 electrically erases all bits simultaneously
using Fowler-Nordheim tunneling. The bytes are pro-
grammed one byte at a time using the EPROM
programming mechanism of hot electron injection.
PRODUCT SELECTOR GUIDE
Family Part Number
Speed Options (V
CC
= 5.0 V
±
10%)
Max Access Time (ns)
CE
#
(E
#
) Access (ns)
OE
#
(G
#
) Access (ns)
-70
70
70
35
-90
90
90
35
Am28F020
-120
120
120
50
-150
150
150
55
-200
200
200
55
BLOCK DIAGRAM
DQ0–DQ7
V
CC
V
SS
V
PP
Erase
Voltage
Switch
Input/Output
Buffers
To Array
WE#
State
Control
Command
Register
CE#
OE#
Program
Voltage
Switch
Chip Enable
Output Enable
Logic
Data Latch
Program/Erase
Pulse Timer
Y-Decoder
Address Latch
Y-Gating
Low V
CC
Detector
X-Decoder
2,097,152
Bit
Cell Matrix
A0–A17
14727F-1
2
Am28F020
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The ordering number (Valid Combination) is
formed by a combination of the following:
AM28F020
-70
J
C
B
OPTIONAL PROCESSING
Blank = Standard Processing
B
= Burn-In
Contact an AMD representative for more information.
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
P = 32-Pin Plastic DIP (PD 032)
J = 32-Pin Rectangular Plastic Leaded Chip
Carrier (PL 032)
E = 32-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 032)
F = 32-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR032)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am28F020
2 Megabit (256 K x 8-Bit) CMOS Flash Memory
Valid Combinations
AM28F020-70
AM28F020-90
AM28F020-120
AM28F020-150
AM28F020-200
PC, PI, PE,
JC, JI, JE,
EC, EI, EE,
FC, FI, FE
Valid Combinations
Valid Combinations list configurations planned to be support-
ed in volume for this device. Consult the local AMD sales of-
fice to confirm availability of specific valid combinations and
to check on newly released combinations.
Am28F020
5
Power technology
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