Chip design faces a variety of challenges in many aspects, which require network and system design expertise as well as chip technology to solve. Ultimately, customers always want to reduce total syst...
With the improvement of FPGA (Field Programmable Gate Array) capacity, function and reliability, its application in modern digital communication systems is becoming more and more extensive. Using FPGA...
[b][color=#000000][font=Arial][font=Arial]1.2.[/font] [/font][font=新宋体]Data width[/font][/color][/b] [align=left][color=#000000] Let's talk about the length of data types. I think this is a defect of ...
Thanko, a Japanese company, recently launched a "covert action equipment" that can usually only be seen in movies: a digital camera that can be disguised as a button. The camera is only the size of a ...
I use GPSOpenDevice in WinCE to open the device first, then GPS_DEVICE pGPSDevice = {0}; pGPSDevice.dwVersion = GPS_VERSION_1; pGPSDevice.dwSize = sizeof(pGPSDevice); use GPSGetDeviceState to get the ...
ZTE
The communication embargo incident has impacted the communication industry and sounded the alarm for the semiconductor industry. Let's follow the embedded editor to learn more about the r...[Details]
1. Purpose In actual product release, if the program stored in the MCU Flash is not protected, some illegal companies may read the program in the Flash through an emulator (J-Link, ST-Link, e...[Details]
The update interrupt initialization configuration of the stm32 advanced timer TIM1 is not much different from that of the ordinary timer. What needs to be paid attention to is the configuration of TI...[Details]
This part of the code in the void SystemClock_Config(void) function in the main file generated by stm32cubemx RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; This bug occurs, and the f...[Details]
Chip: STM32F107VCT6 Application Pin: THOUSANDS, RMII STM32CubeMX is very convenient to use ETH. The software comes with LWIP and configuration. This time, STM32F107VCT6+DP83848CVV is used. The MII a...[Details]
The goal of this article is to build a TCP client based on the previous project that can ping the PC, and can actively send data to the PC, and can also send and receive data with the PC, and display...[Details]
Function List and Notes (lower-level driver part) 1. IO port initialization: control IO and communication IO. Control includes power control, reset and low power mode. Communication is the serial po...[Details]
I slightly changed the lyrics of Yu Quan's song "Running", which seems to be
a reflection of the current state of
Huawei Cloud
. At the annual Huawei Analyst Conference held on April 17,
Zh...[Details]
Nowadays, everyone is saying that "technology is people-oriented". The essence of the development of technology is to serve the improvement of the quality of life of human beings. Automated driving...[Details]
The article is written for LPC2148, but it is also applicable to Samsung's 44B0 chip. You only need to select S3C44B0 as the corresponding CPU when selecting it. JLINK debugging experience un...[Details]
sprintf is a function in the C language library that converts data types. There is a situation where In 51 MCU, define unsigned char temp; Then I want to use the serial port to print out temp in deci...[Details]
According to the description provided in the official manual of ST, it is not difficult to see that the ADC analog watchdog is actually that the user can set an upper and lower limit of the AD value...[Details]
6MHz crystal oscillator, using timer counter 1, using interrupt mode, through P1.0 to make a light emitting diode turn on for 100ms, turn off for 300ms, and repeat. Assembly programming is used to ac...[Details]
Since 2018, the field of artificial intelligence chips has been very lively. Especially in China, the rich vertical application scenarios have provided fertile ground for the development of AI chip...[Details]
Requirements: Set timer T1 as an external event counter, count 500 pulses every time, then switch T1 to timing mode and output a positive pulse with a width of 10ms at P1.2. Over and over again. A...[Details]
FPGA/CPLD
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