1 GSPS
Direct Digital Synthesizer
AD9858
FEATURES
1 GSPS internal clock speed
Up to 2 GHz input clock (selectable divide-by-2)
Integrated 10-bit D/A converter
Phase noise < 145 dBc/Hz @ 1 kHz offset
Output frequency = 100 MHz (DAC output)
32-bit programmable frequency register
Simplified 8-bit parallel and SPI® serial control interface
Automatic frequency sweeping capability
4 frequency profiles
3.3 V power supply
Power dissipation 2 W typical
Integrated programmable charge pump and phase
frequency detector with fast lock circuit
Isolated charge pump supply up to 5 V
Integrated 2 GHz mixer
GENERAL DESCRIPTION
The AD9858 is a direct digital synthesizer (DDS) featuring a
10-bit DAC operating up to 1GSPS. The AD9858 uses advanced
DDS technology, coupled with an internal high speed, high
performance D/A converter to form a digitally programmable,
complete high frequency synthesizer capable of generating a
frequency-agile analog output sine wave at up to 400+ MHz.
The AD9858 is designed to provide fast frequency hopping and
fine tuning resolution (32-bit frequency tuning word). The
frequency tuning and control words are loaded into the AD9858
via parallel (8-bit) or serial loading formats. The AD9858
contains an integrated charge pump (CP) and phase frequency
detector (PFD) for synthesis applications requiring the
combination of a high speed DDS along with phase-locked loop
(PLL) functions. An analog mixer is also provided on-chip for
applications requiring the combination of a DDS, PLL, and
mixer, such as frequency translation loops, tuners, and so on.
The AD9858 also features a divide-by-2 on the clock input,
allowing the external clock to be as high as 2 GHz.
The AD9858 is specified to operate over the extended industrial
temperature range of –40°C to +85°C.
APPLICATIONS
VHF/UHF LO synthesis
Tuners
Instrumentation
Agile clock synthesis
Cellular base station hopping synthesizer
Radar
Sonet/SDH clock synthesis
LO
DIV
PD
CP
CPISET
FREQUENCY
ACCUMULATOR
IF
FUNCTIONAL BLOCK DIAGRAM
RF
÷M
÷N
CHARGE
PUMP
ANALOG
MULTIPLIER
PHASE
DETECTOR
AD9858
DIGITAL PLL
PHASE
ACCUMULATOR
DACISET
32
15
15
PHASE-TO-
AMPLITUDE
CONVERSION
10
DAC
I
OUT
I
OUT
FREQUENCY
ACCUMULATOR
RESET
PHASE
ACCUMULATOR
RESET
DELTA
FREQUENCY
WORD
DELTA
FREQUENCY
RAMP RATE
FREQUENCY
TUNING
WORD
14
PHASE
OFFSET
ADJUST
DAC CLOCK
32
RESET
32
TIMING AND CONTROL LOGIC
FUD
SYNCLK
CONTROL REGISTERS
SYNC
POWER-
DOWN
LOGIC
÷8
M
U
X
÷2
REFCLK
REFCLK
03166-A-001
PROFILE I/O PORT
SELECT (SER/PAR)
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2003 Analog Devices, Inc. All rights reserved.
AD9858
TABLE OF CONTENTS
Features .......................................................................................... 1
Applications................................................................................... 1
General Description..................................................................... 1
Functional Block Diagram .......................................................... 1
AD9858—Electrical Specifications ................................................ 3
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration............................................................................. 7
Pin Function Descriptions .............................................................. 8
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 15
Overview ..................................................................................... 15
Component Blocks..................................................................... 15
Modes of Operation................................................................... 17
Synchronization.......................................................................... 19
Programming the AD9858........................................................ 21
AD9858 Application Suggestions............................................. 29
Evaluation Boards ...................................................................... 30
Outline Dimensions ....................................................................... 31
Warning ....................................................................................... 31
Ordering Guide .......................................................................... 31
REVISION HISTORY
11/03—Data Sheet Changed from a REV. 0 to a REV. A
Changes to SPECIFICATIONS........................................................ 5
Moved ESD Caution to ..................................................................... 6
Moved Pin Configuration to ............................................................ 7
Moved Pin Function Description to ............................................... 8
Changes to Equations........................................................................ 19
Changes to Delta Frequency Ramp Rate Word (DFRRW) .......... 27
Rev. A | Page 2 of 32
AD9858
AD9858—ELECTRICAL SPECIFICATIONS
Table 1. Unless otherwise noted, V
DD
= 3.3 V ± 5%, CPV
DD
= 5 V ± 5%, R
SET
= 2 kΩ, C
PISET
= 2.4 kΩ,
Reference Clock Frequency = 1 GHz.
Parameter
REF CLOCK INPUT CHARACTERISTICS
1, 2
Reference Clock Frequency Range (Divider Off)
Reference Clock Frequency Range (Divider On)
Duty Cycle @ 1 GHz
Input Capacitance
Input Impedance
Input Sensitivity
Temp
Full
Full
25°C
25°C
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
VI
VI
V
V
IV
VI
Min
10
20
42
Typ
Max
1000
2000
58
Unit
MHz
MHz
%
pF
Ω
dBm
Bits
mA
% FS
µA
LSB
LSB
kΩ
V
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
50
3
1500
–20
10
20
+5
DAC OUTPUT CHARACTERISTICS
Resolution
Full-Scale Output Current
Gain Error
Output Offset
Differential Nonlinearity
Integral Nonlinearity
Output Impedance
Voltage Compliance Range
Wideband SFDR (DC to Nyquist)
40 MHz F
OUT
100 MHz F
OUT
180 MHz F
OUT
360 MHz F
OUT
180 MHz F
OUT
(700 MHz REFCLK)
Narrow-Band SFDR3
3
40 MHz F
OUT
(±15 MHz)
40 MHz F
OUT
(±1 MHz)
40 MHz F
OUT
(±50 kHz)
100 MHz F
OUT
(±15 MHz)
100 MHz F
OUT
(±1 MHz)
100 MHz F
OUT
(±50 kHz)
180 MHz F
OUT
(±15 MHz)
180 MHz F
OUT
(±1 MHz)
180 MHz F
OUT
(±50 kHz)
360 MHz F
OUT
(±15 MHz)
360 MHz F
OUT
(±1 MHz)
360 MHz F
OUT
(±50 kHz)
180 MHz F
OUT
(±15 MHz) (700 MHz REFCLK)
180 MHz F
OUT
(±1 MHz) (700 MHz REFCLK)
180 MHz F
OUT
(±50 kHz) (700 MHz REFCLK)
OUTPUT PHASE NOISE CHARACTERISTICS (@ 103 MHz I
OUT
)
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
OUTPUT PHASE NOISE CHARACTERISTICS (@ 403 MHz I
OUT
)
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
5
–10
40
+10
15
1
1.5
AV
DD
+ 0.5
60
54
53
50
52
82
87
88
81
82
86
74
84
85
75
85
86
65
80
84
–147
–150
–152
–133
–137
–140
VI
VI
VI
VI
VI
VI
V
V
V
V
IV
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
0.5
1
100
AV
DD
– 1.5
Rev. A | Page 3 of 32
AD9858
Parameter
OUTPUT PHASE NOISE CHARACTERISTICS (@ 100 MHz I
OUT
with 700 MHz REFCLK)
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
PHASE DETECTOR AND CHARGE PUMP
Phase Detector Frequency
Phase Detector Frequency (Divide-by-4 Enabled)
4
Charge Pump Sink and Source Current
5
Fast Lock Current (Acquisition Only)
Open-Loop Current (Acquisition Only)
Sink and Source Current Absolute Accuracy
6
Sink and Source Current Matching
6
Input Sensitivity PD
IN
and DIV
IN
(50 Ω)
7
Input Impedence PD
IN
and DIV
IN
(Single-Ended)
Phase Noise @ 100 MHz Input Frequency
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
Charge Pump Output Range
8
MIXER
IF
OUT9
F
RF
F
LO
Conversion Gain
LO Level
RF Level
Input IP3
1 dB Input Compression Power
10
Input Impedance (Single-Ended)
LO
RF
LOGIC INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
POWER SUPPLY
P
DISS
(Worst-Case Conditions—Everything on
P
FD
Input Frequency 150 MHz)
P
DISS
(DAC and DDS Core Only Worst-Case)
P
DISS
(Power-Down Mode)
P
DISS
Mixer Only
P
DISS
PFD and CP (@ 100 MHz) Only
Temp
Test
Level
Min
Typ
Max
Unit
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
V
V
V
V
V
V
VI
VI
VI
VI
VI
V
V
IV
V
V
V
V
V
V
VI
VI
VI
VI
VI
VI
VI
V
V
VI
VI
VI
VI
V
VI
VI
VI
VI
VI
–125
–140
–148
–150
–150
–150
150
400
4
7
30
2.5
1
–15
1
110
140
148
CPV
DD
400
2
2
0.0
–10
–20
5
–3
3.5
+5
9
0
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
MHz
MHz
mA
mA
mA
%
%
dBm
kΩ
dBc/Hz
dBc/Hz
dBc/Hz
V
MHz
GHz
GHz
dB
dBm
dBm
dBm
dBm
kΩ
kΩ
V
V
µA
µA
pF
W
W
mW
mW
mW
1
1
2.0
0.8
12
12
3
2
1.7
65
60
350
2.5
2
100
75
435
Rev. A | Page 4 of 32
AD9858
Parameter
TIMING CHARACTERISTICS
Serial Control Bus
Maximum Frequency
Minimum Clock Pulse Width Low (t
PWL
)
Minimum Clock Pulse Width High (t
PWH
)
Maximum Clock Rise/Fall Time
Minimum Data Setup Time (t
DS
)
Mimimum Data Hold Time (t
DH
)
Maximum Data Valid Time (t
DV
)
Parallel Control Bus
WR Minimum Low Time
WR Minimum High Time
WR Minimum Period
Address to WR Setup (T
ASU
)
Address to WR Setup (T
AHU
)
Data to WR Setup (T
DSU
)
Data to WR Hold (T
DHU
)
Miscellaneous Timing Specifications
REFCLK to SYNCLK
FUD to SYNCLK Setup Time
FUD to SYNCLK Hold Time
REFCLK to SYNCLK Delay
FUD Rising Edge to Frequency Change
Single Tone Mode
Linear Sweep Mode
FUD Rising Edge to Phase Offset Change
Temp
Test
Level
Min
Typ
Max
Unit
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
25°C
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
V
IV
IV
IV
IV
IV
IV
10
5.5
15
1
7
0
20
3
6
9
3
0
3.5
0
2.5
4
0
2.5
3
83
99
83
MHz
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
sysclk
cycles
sysclk
cycles
sysclk
cycles
1
2
The reference clock input is configured to accept a differential or single-ended sine wave input or a 3 V CMOS-level pulse input.
REFCLK input is internally dc biased. AC coupling should be used.
3
Reference clock frequency is selected to ensure second harmonic is out of the bandwidth of interest.
4
PD inputs sent @ 400 MHz, with divide-by-4 enabled.
5
The charge pump current is programmable in eight discrete steps, minimum value assumes current sharing.
6
For 0.75 V < V
CP
< CPV
DD
– 0.75 V.
7
These differential inputs are internally dc biased. AC coupling should be used.
8
The charge pump supply voltage can range from 4.75 V to 5.25 V.
9
Output interface is differential open collector.
10
For 1 dB output compression; input power measured at 50 Ω.
Rev. A | Page 5 of 32
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