SN54BCT374, SN74BCT374
OCTAL EDGE-TRIGGERED D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS019C – SEPTEMBER 1988 – REVISED MARCH 2003
D
D
D
D
Operating Voltage Range of 4.5 V to 5.5 V
State-of-the-Art BiCMOS Design
Significantly Reduces I
CCZ
Full Parallel Access for Loading
Buffered Control Inputs
SN54BCT374 . . . J OR W PACKAGE
SN74BCT374 . . . DW, N, OR NS PACKAGE
(TOP VIEW)
D
D
3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
SN54BCT374 . . . FK PACKAGE
(TOP VIEW)
1D
1Q
OE
V
CC
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
2D
2Q
3Q
3D
4D
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
8Q
8D
7D
7Q
6Q
6D
description/ordering information
These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight flip-flops of the ’BCT374 devices are edge-triggered D-type flip-flops. On the positive transition of the
clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without
need for interface or pullup components. The output-enable (OE) input does not affect internal operations of
the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance
state.
ORDERING INFORMATION
TA
PDIP – N
0°C to 70°C
SOIC – DW
SOP – NS
CDIP – J
–55°C to 125°C
CFP – W
LCCC – FK
PACKAGE†
Tube
Tube
Tape and reel
Tape and reel
Tube
Tube
Tube
ORDERABLE
PART NUMBER
SN74BCT374N
SN74BCT374DW
SN74BCT374DWR
SN74BCT374NSR
SNJ54BCT374J
SNJ54BCT374W
SNJ54BCT374FK
TOP-SIDE
MARKING
SN74BCT374N
BCT374
BCT374
SNJ54BCT374J
SNJ54BCT374W
SNJ54BCT374FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
•
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4Q
GND
CLK
5Q
5D
1
SN54BCT374, SN74BCT374
OCTAL EDGE-TRIGGERED D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS019C – SEPTEMBER 1988 – REVISED MARCH 2003
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
L
L
L
H
CLK
↑
↑
H or L
X
D
H
L
X
X
OUTPUT
Q
H
L
Q0
Z
logic diagram (positive logic)
OE
CLK
1D
1
11
C1
3
1D
2
1Q
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the disabled or power-off state, V
O
. . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Voltage range applied to any output in the high state, V
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
CC
Input clamp current, I
IK
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA
Current into any output in the low state: SN54BCT374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74BCT374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Package thermal impedance,
θ
JA
(see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54BCT374, SN74BCT374
OCTAL EDGE-TRIGGERED D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS019C – SEPTEMBER 1988 – REVISED MARCH 2003
recommended operating conditions (see Note 3)
SN54BCT374
MIN
VCC
VIH
VIL
IIK
IOH
IOL
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
4.5
2
0.8
–18
–2
48
NOM
5
MAX
5.5
SN74BCT374
MIN
4.5
2
0.8
–18
–15
64
NOM
5
MAX
5.5
UNIT
V
V
V
mA
mA
mA
TA
Operating free-air temperature
–55
125
0
70
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VCC = 4.5 V,
VCC = 4.5 V
TEST CONDITIONS
II = –18 mA
IOH = –3 mA
IOH = –12 mA
IOH = –15 mA
IOL = 48 mA
IOL = 64 mA
VI = 5.5 V
VI = 2.7 V
VI = 0.5 V
VO = 0
VO = 2.7 V
VO = 0.5 V
37
2
5
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
6
–100
SN54BCT374
MIN TYP†
MAX
–1.2
2.4
2
3.3
3.2
2
0.38
0.55
0.42
0.4
20
–0.6
–225
50
–50
60
5
8
37
2
5
6
10
–100
0.55
0.4
20
–0.6
–225
50
–50
60
5
8
3.1
V
mA
µA
mA
mA
µA
µA
mA
mA
mA
pF
pF
2.4
3.3
V
SN74BCT374
MIN TYP†
MAX
–1.2
UNIT
V
VOL
II
IIH
IIL
IOS‡
IOZH
IOZL
ICCL
ICCH
ICCZ
Ci
Co
VCC = 4 5 V
4.5
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V
VCC = 5.5 V
VCC = 5.5 V
VCC = 5 V,
VCC = 5 V,
10
† All typical values are at VCC = 5 V, TA = 25°C.
‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
POST OFFICE BOX 655303
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DALLAS, TEXAS 75265
3
SN54BCT374, SN74BCT374
OCTAL EDGE-TRIGGERED D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS019C – SEPTEMBER 1988 – REVISED MARCH 2003
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 5 V,
TA = 25°C
MIN
fclock
tw
tsu
th
Clock frequency
Pulse duration
Setup time before CLK↑
Hold time after CLK↑
CLK high
Data high or low
Data high or low
7
6.5
0
MAX
70
8
6.5
0
SN54BCT374
MIN
MAX
70
7
6.5
0
SN74BCT374
MIN
MAX
70
MHz
ns
ns
ns
UNIT
switching characteristics (see Figure 1)
VCC = 5 V,
CL = 50 pF,
R1 = 500
Ω,
R2 = 500
Ω,
TA = 25°C
’BCT374
MIN
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
70
CLK
Q
Q
Q
2
2
1
1
1
7.2
7.1
8.3
8.6
4.7
9.1
8.8
10.1
10.6
6.3
TYP
MAX
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500
Ω,
R2 = 500
Ω,
TA = MIN to MAX†
SN54BCT374
MIN
70
2
2
1
1
1
11.6
10.6
12.7
13
7.1
MAX
SN74BCT374
MIN
70
2
2
1
1
1
1
10.6
10
12.3
12.7
6.8
6.8
MAX
MHz
ns
ns
ns
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
UNIT
OE
OE
tPLZ
1
4.8
6.3
1
7.5
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
4
POST OFFICE BOX 655303
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DALLAS, TEXAS 75265
SN54BCT374, SN74BCT374
OCTAL EDGE-TRIGGERED D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS019C – SEPTEMBER 1988 – REVISED MARCH 2003
PARAMETER MEASUREMENT INFORMATION
7 V (tPZL, tPLZ, O.C.)
Open
(all others)
S1
From Output
Under Test
CL
(see Note A)
R1
Test
Point
R1
From Output
Under Test
CL
(see Note A)
R2
RL = R1 = R2
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE AND OPEN-COLLECTOR OUTPUTS
High-Level
Pulse
(see Note B)
3V
1.5 V
tw
0V
tsu
Data Input
(see Note B)
1.5 V
th
3V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
Low-Level
Pulse
1.5 V
1.5 V
0V
3V
1.5 V
0V
Timing Input
(see Note B)
3V
1.5 V
3V
Input
(see Note B)
tPLH
In-Phase
Output
(see Note D)
tPHL
Out-of-Phase
Output
(see Note D)
1.5 V
3V
1.5 V
1.5 V
0V
tPHL
VOH
1.5 V
1.5 V
VOL
tPLH
VOH
1.5 V
VOL
Waveform 2
(see Notes C and D)
Waveform 1
(see Notes C and D)
Output
Control
(low-level enable)
tPZL
1.5 V
1.5 V
1.5 V
0V
tPLZ
3.5 V
VOL
tPHZ
tPZH
VOH
1.5 V
0.3 V
0V
0.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (see Note D)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
≤
10 MHz, tr = tf
≤
2.5 ns, duty cycle = 50%.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
E. When measuring propagation delay times of 3-state outputs, switch S1 is open.
F. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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5
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