SSM2303N
P-CHANNEL ENHANCEMENT-MODE POWER MOSFET
Simple drive requirement
Small package outline
Surface-mount device
S
D
BV
DSS
R
DS(ON)
I
D
-30V
240mΩ
- 1.7A
Description
SOT-23
G
D
Power MOSFETs from
Silicon Standard
provide the
designer with the best combination of fast switching,
low on-resistance and cost-effectiveness.
G
S
Absolute Maximum Ratings
Symbol
V
DS
V
GS
I
D
@ T
A
=25°C
I
D
@ T
A
=70°C
I
DM
P
D
@ T
A
=25°C
T
STG
T
J
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
3
Continuous Drain Current
3
Pulsed Drain Current
1,2
Total Power Dissipation
Linear Derating Factor
Storage Temperature Range
Operating Junction Temperature Range
Rating
- 30
± 20
-1.7
-1.4
-10
1.25
0.01
-55 to 150
-55 to 1 50
Units
V
V
A
A
A
W
W/°C
°C
°C
Thermal Data
Symbol
Rthj-amb
Parameter
Thermal Resistance Junction-ambient
3
Value
Max.
100
Unit
°C/W
Rev.2.02 3/16/2004
www.SiliconStandard.com
1 of 6
SSM2303N
Electrical Characteristics @ T
j
=25
o
C (unless otherwise specified)
Symbol
BV
DSS
∆
BV
DSS
/
∆
T
j
Parameter
Drain-Source Breakdown Voltage
Test Conditions
V
GS
=0V, I
D
=-250uA
Min.
-30
-
-
-
-1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Typ.
-
-0.1
Max. Units
-
-
240
460
-
-
-1
-10
±100
-
-
-
-
-
-
-
-
-
-
V
V/°C
mΩ
mΩ
V
S
uA
uA
nA
nC
nC
nC
ns
ns
ns
ns
pF
pF
pF
Breakdown Voltage Temperature Coefficient
Reference to 25°C, I
D
=-1mA
R
DS(ON)
Static Drain-Source On-Resistance
V
GS
=-10V, I
D
=-1.7A
V
GS
=-4.5V, I
D
=-1.3A
-
-
-
2
-
-
-
6.2
1.4
0.3
20
20
35
20
230
130.4
40
V
GS(th)
g
fs
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
Gate Threshold Voltage
Forward Transconductance
Drain-Source Leakage Current (T
j
=25
o
C)
Drain-Source Leakage Current (T
j
=55
o
C)
V
DS
=V
GS
, I
D
=-250uA
V
DS
=-10V, I
D
=-1.7A
V
DS
=-30V, V
GS
=0V
V
DS
=-30V, V
GS
=0V
V
GS
=
±
20V
I
D
=-1.7A
V
DS
=-15V
V
GS
=-10V
V
DS
=-15V
I
D
=-1A
R
G
=6Ω
,V
GS
=-10V
R
D
=6Ω
V
GS
=0V
V
DS
=-15V
f=1.0MHz
Gate-Source Leakage
Total Gate Charge
2
Gate-Source Charge
Gate-Drain ("Miller") Charge
Turn-on Delay Time
2
Rise Time
Turn-off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Source-Drain Diode
Symbol
I
S
I
SM
V
SD
Parameter
Continuous Source Current ( Body Diode )
Test Conditions
V
D
=V
G
=0V , V
S
=-1.2V
I
S
=-1.25A, V
GS
=0V
Min.
-
-
-
Typ.
-
-
-
Max. Units
-1.25
-10
-1.2
A
A
V
Pulsed Source Current ( Body Diode )
1
Forward On Voltage
2
Notes:
1.Pulse width limited by Max. junction temperature.
2.Pulse width <300us , duty cycle <2%.
3.Surface mounted on FR4 board, t < 5 sec.
Rev.2.02 3/16/2004
www.SiliconStandard.com
2 of 6
SSM2303N
10
10
T
C
=25
o
C
8
-10V
-8.0V
-6.0V
-5.0V
T
C
=150
o
C
8
-10V
-8.0V
-6.0V
-5.0V
-I
D
, Drain Current (A)
-I
D
, Drain Current (A)
6
6
4
4
V
GS
=-4.0V
2
V
GS
=-4.0V
2
0
0
2
4
6
0
0
2
4
6
-V
DS
, Drain-to-Source Voltage (V)
-V
DS
, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
250
1.8
I
D
=-1.7A
T
C
=25
℃
I
D
=-1.7A
1.6
V
GS
= -10V
Normalized R
DS(ON)
200
1.4
R
DS(ON)
(m
Ω
)
1.2
150
1
0.8
100
3
4
5
6
7
8
9
10
11
0.6
-50
0
50
100
150
-V
GS
(V)
T
j
, Junction Temperature (
o
C)
Fig 3. On-Resistance vs. Gate Voltage
Fig 4. Normalized On-Resistance
vs. Junction Temperature
Rev.2.04 3/16/2004
www.SiliconStandard.com
3 of 6
SSM2303N
2
2
1.5
1.5
-I
D
, Drain Current (A)
P
D
(W)
1
1
0.5
0.5
0
25
50
75
100
125
150
0
0
50
100
150
T
c
, Case Temperature ( C)
o
T
c
(
o
C)
Fig 5. Maximum Drain Current vs.
Case Temperature
Fig 6. Typical Power Dissipation
100
1
Duty Factor = 0.5
10
Normalized Thermal Response (R
thja
)
0.2
-I
D
(A)
0.1
0.1
1ms
1
0.05
P
DM
t
Single Pulse
T
Duty Factor = t/T
Peak T
j
= P
DM
x R
thja
+ T
a
10ms
T
c
=25 C
Single Pulse
0.1
0.1
1
10
100
0.02
o
100ms
1s
0.01
0.0001
0.001
0.01
0.1
1
10
100
-V
DS
(V)
t , Pulse Width (s)
Fig 7. Maximum Safe Operating Area
Fig 8. Effective Transient Thermal Impedance
Rev.2.02 3/16/2004
www.SiliconStandard.com
4 of 6
SSM2303N
14
1000
f=1.0MHz
12
I
D
= -1.7A
V
DS
= -15V
Ciss
-V
GS
, Gate to Source Voltage (V)
10
8
C (pF)
100
Coss
6
Crss
4
2
0
0
1
2
3
4
5
6
7
8
10
1
8
15
22
29
Q
G
, Total Gate Charge (nC)
-V
DS
(V)
Fig 9. Gate Charge Characteristics
Fig 10. Typical Capacitance Characteristics
100
2.4
10
T
j
=150
o
C
-I
F
(A)
T
j
=25
o
C
1
1.8
-V
GS(th)
(V)
1.2
0.6
1.3
1.5
-50
0
0
0.1
0.3
0.5
0.7
0.9
1.1
0
50
100
150
-V
SD
(V)
T
j
, Junction Temperature (
o
C)
Fig 11. Forward Characteristic of
Reverse Diode
Fig 12. Gate Threshold Voltage vs.
Junction Temperature
Rev.2.02 3/16/2004
www.SiliconStandard.com
5 of 6
京公网安备 11010802033920号
EEWORLD
