M7040N-066ZA1 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Wireless rf/communication> Telecom circuit> M7040N-066ZA1

M7040N-066ZA1: DescriptionSPECIALTY TELECOM CIRCUIT, PBGA388, 35 X 35 MM, 1.27 MM PITCH, PLASTIC, BGA-388; CategoryWireless rf/communication Telecom circuit; File Size1MB，159 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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M7040N-066ZA1 Overview

SPECIALTY TELECOM CIRCUIT, PBGA388, 35 X 35 MM, 1.27 MM PITCH, PLASTIC, BGA-388

M7040N-066ZA1 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	STMicroelectronics
Parts packaging code	BGA
package instruction	35 X 35 MM, 1.27 MM PITCH, PLASTIC, BGA-388
Contacts	388
Reach Compliance Code	not_compliant
JESD-30 code	S-PBGA-B388
JESD-609 code	e0
length	35 mm
Number of functions	1
Number of terminals	388
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA388,26X26,50
Package shape	SQUARE
Package form	GRID ARRAY
power supply	1.5,2.5/3.3 V
Certification status	Not Qualified
Maximum seat height	2.46 mm
Nominal supply voltage	1.5 V
surface mount	YES
Telecom integrated circuit types	TELECOM CIRCUIT
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	35 mm

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M7040N

64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE

PRELIMINARY DATA

FEATURES SUMMARY

64K DATA ENTRIES IN 72-BIT MODE

Figure 1. 388-ball PBGA Package

TABLE MAY BE PARTITIONED INTO UP TO

EIGHT (8) OCTANTS

(Data entry width in each octant is configurable

as 36, 72, 144, or 288 bits.)

UP TO 100 MILLION SUSTAINED SEARCHES

PER SECOND IN 72-BIT and 144-BIT

CONFIGURATIONS

UP TO 50 MILLION SEARCHES PER

SECOND IN 36-BIT and 288-BIT

CONFIGURATIONS

SEARCHES ANY SUB-FIELD IN A SINGLE

CYCLE

OFFERS BIT-BY-BIT and GLOBAL MASKING

SYNCHRONOUS, PIPELINED OPERATION

UP TO 31 SEARCH ENGINES CASCADABLE

WITHOUT PERFORMANCE DEGRADATION

WHEN CASCADED, THE DATABASE

ENTRIES CAN SCALE FROM 496K TO 3968K

DEPENDING ON THE WIDTH OF THE ENTRY

GLUELESS INTERFACE TO INDUSTRY-

STANDARD SRAMS

SIMPLE HARDWARE INSTRUCTION

INTERFACE

IEEE 1149.1 TEST ACCESS PORT

OPERATING SUPPLY VOLTAGES INCLUDE:

(Operating Core Supply Voltage) = 1.5V for

66 and 83MSPS; 1.65V for 100MSPS

DDQ

(Operating Supply Voltage for I/O) = 2.5

or 3.3V

388 PBGA, 35mm x 35mm

388-ball PBGA

35mm x 35mm

May 2002

1/159

M7040N

TABLE OF CONTENTS

DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Product Range (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Switch/Router Implementation Using the M7040N (Figure 2.) . . . . .

Signal Names (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Connections (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

M7040N Block Diagram (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . .

.......

......

.....7

.....8

.....9

. . . . 10

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Absolute Maximum Ratings (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

DC and AC Measurement Conditions (Table 4.) . . . . . . . . . . . . . . . .

M7040N 1.8, 2.5, or 3.3V AC Testing Load (Figure 5.) . . . . . . . . . . .

M7040N 1.8, 2.5, or 3.3V Input Waveform (Figure 6.) . . . . . . . . . . .

M7040N 1.8, 2.5, or 3.3V I/O Output Load Equivalent (Figure 7.) . .

Capacitance (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DC Characteristics (Table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AC Timing Waveforms with CLK2X (Figure 8.) . . . . . . . . . . . . . . . . .

AC Timing Waveforms with CLK1X (Figure 9.) . . . . . . . . . . . . . . . . .

AC Timing Parameters with CLK2X (Table 7.) . . . . . . . . . . . . . . . . .

AC Timing Parameters with CLK1X (Table 8.) . . . . . . . . . . . . . . . . .

.......

......

. . . . 12

. . . . 13

. . . . 14

. . . . 15

. . . . 16

. . . . 17

. . . . 18

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Command Bus and DQ Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Database Entry (Data Array and Mask Array) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Arbitration Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Pipeline and SRAM Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Full Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Connection Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

CLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Clocks (CLK2X and PHS_L) (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Clocks (CLK1X) (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Clocks for All Timing Diagrams (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

PLL USAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

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M7040N

REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Register Overview (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Comparand Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Comparand Register Selection During SEARCH and LEARN Instructions (Figure 13.) . . . . . . . . . 23

Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Addressing the Global Masks Register Array (Figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

SEARCH-Successful Registers (SSR[0:7]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

SEARCH-Successful Register (SSR) Description (Table 10.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

The Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Command Register Field Descriptions (Table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

The Information Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Information Register Field Descriptions (Table 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

The Read Burst Address Register (RBURREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Read Burst Register Description (Table 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

The Write Burst Address Register (WBURREG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Write Burst Register Description (Table 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

The NFA Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

NFA Register (Table 15.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

SEARCH ENGINE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Data and Mask Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

M7040N Database Width Configuration (Figure 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Bit Position Match (Table 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Multi-width Configuration Example (Figure 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

M7040N Data and Mask Array Addressing (Figure 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

COMMAND CODES AND PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Commands and Command Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Command Codes (Table 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Command Parameters (Table 18.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

READ COMMAND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Single Location READ Cycle Timing (Figure 18.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Burst READ of the Data and Mask Arrays (BLEN = 4) (Figure 19.) . . . . . . . . . . . . . . . . . . . . . . . . 33

READ Command Parameters (Table 19.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Data and Mask Array, SRAM Read Address Format (Table 20.) . . . . . . . . . . . . . . . . . . . . . . . . . . 34

READ Address Format for Internal Registers (Table 21.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

READ Address Format for Data and Mask Arrays (Table 22.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3/159

M7040N

WRITE COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Single Location WRITE Cycle Timing (Figure 20.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Burst WRITE of the Data and Mask Arrays (BLEN = 4) (Figure 21.). . . . . . . . . . . . . . . . . . . . . . . . 37

(Single) WRITE Address Format for Data and Mask Arrays or SRAM (Table 23.) . . . . . . . . . . . . . 37

WRITE Address Format for Internal Registers (Table 24.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

WRITE Address Format for Data and Mask Array (Burst Write) (Table 25.) . . . . . . . . . . . . . . . . . . 38

Parallel WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

SEARCH COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

72-bit Configuration with Single Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Hardware Diagram for a Table with One Device (Figure 22.) . . . . . . . . . . . . . . . . . . .

72-Bit Configuration SEARCH Timing Diagram for One Device (Figure 23.) . . . . . . .

x72 Table with One Device (Figure 24.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Latency of SEARCH from Instruction to SRAM Access Cycle, 72-bit (Table 26.) . . . .

Shift of SSF and SSV from SADR (Table 27.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

......

. . . . 38

. . . . 39

. . . . 40

. . . . 41

. . . . 42

. . . . 43

. . . . 44

. . . . 45

. . . . 48

72-bit SEARCH on Tables Configured as x72 Using up to Eight M7040N Devices . . . . .

Hit/Miss Assumption (Table 28.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Hardware Diagram for a Table with Eight Devices (Figure 25.) . . . . . . . . . . . . . . . . . . . . . . .

x72 Table with Eight Devices (Figure 26.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timing Diagrams for x72 Using up to Eight M7040N Devices. . . . . . . . . . . . . . . . . . . . . . . . .

Latency of SEARCH from Instruction to SRAM Access Cycle (Table 29.) . . . . . . . . . . . . . . .

Shift of SSF and SSV from SADR (Table 30.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

72-bit Search on Tables Configured as x72 Using Up To 31 M7040N Devices . . . . . . . . . . . . 48

Hit/Miss Assumption (Table 31.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Hardware Diagram for a Table with 31 Devices (Figure 30.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Hardware Diagram for a Block of Up To Eight Devices (Figure 31.) . . . . . . . . . . . . . . . . . . . . . . . . 51

x72 Table with 31 Devices (Figure 32.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Timing Diagrams for x72 Using Up To 31 M7040N Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Latency of SEARCH from Instruction to SRAM Access Cycle (Table 32.) . . . . . . . . . . . . . . . . . . . 64

Shift of SSF and SSV from SADR (Table 33.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

144-bit Configuration with Single Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Hardware Diagram for a Table with 1 Device (Figure 44.) . . . . . . . . . . . . . . . . . . . . .

Timing Diagram for a 144-bit SEARCH for 1 Device (Figure 45.) . . . . . . . . . . . . . . . .

x144 Table with One Device (Figure 46.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Latency of SEARCH from Instruction to SRAM Access Cycle, 144-bit (Table 34.). . .

Shift of SSF and SSV from SADR (Table 35.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

......

. . . . 64

. . . . 65

. . . . 66

. . . . 67

144-bit Search on Tables Configured as x144 Using Up to Eight M7040N Devices . . . . . . . . 68

Hit/Miss Assumption (Table 36.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Hardware Diagram for a Table with Eight Devices (Figure 47.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

x144 Table with Eight Devices (Figure 48.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Timing Diagrams for x144 Using Up to Eight M7040N Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Latency of SEARCH from Instruction to SRAM Access Cycle, 144-bit (Table 37.). . . . . . . . . . . . . 74

Shift of SSF and SSV from SADR (Table 38.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4/159

M7040N

144-bit Search on Tables Configured as x144 Using Up to 31 M7040N Devices. . . . . . . . . . . 74

Hit/Miss Assumption (Table 39.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Hardware Diagram for a Table with 31 Devices (Figure 52.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Hardware Diagram for a Block of Up to Eight Devices (Figure 53.) . . . . . . . . . . . . . . . . . . . . . . . . 77

x144 Table with 31 Devices (Figure 54.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Timing Diagrams for x144 Using Up to 31 M7040N Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Latency of SEARCH from Instruction to SRAM Access Cycle, 144-bit (Table 40.). . . . . . . . . . . . . 90

Shift of SSF and SSV from SADR (Table 41.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

288-bit SEARCH on Tables Configured as x288 Using a Single M7040N Device . . . . . . . . . . 90

Hardware Diagram for a Table with One Device (Figure 66.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Timing Diagram for 288-bit SEARCH (One Device) (Figure 67.) . . . . . . . . . . . . . . . . . . . . . . . . . . 92

x288 Table with One Device (Figure 68.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Latency of SEARCH from Cycles C and D to SRAM Access Cycle (Table 42.) . . . . . . . . . . . . . . . 93

Shift of SSF and SSV from SADR (Table 43.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

288-bit SEARCH on Tables x288-configured Using Up to Eight M7040N Devices . . . . . . . . . 94

Hit/Miss Assumption (Table 44.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Hardware Diagram for a Table with Eight Devices (Figure 69.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

x288 Table with Eight Devices (Figure 70.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Timing Diagrams for x288-configured Using Up to Eight M7040N Devices . . . . . . . . . . . . . . . . . . 98

Latency of SEARCH from Cycles C and D to SRAM Access Cycle, 288-bit (Table 45.). . . . . . . . 101

Shift of SSF and SSV from SADR (Table 46.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

288-bit Search on Tables Configured as x288 Using Up to 31 M7040N Devices. . . . . . . . . . 101

Hit/Miss Assumption (Table 47.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Hardware Diagram for a Table with 31 Devices (Figure 74.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Hardware Diagram for a Block of Up to Eight Devices (Figure 75.) . . . . . . . . . . . . . . . . . . . . . . . 104

x288 Table with 31 Devices (Figure 76.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Timing Diagrams for x288 Using Up to 31 M7040N Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Latency of SEARCH from Cycles C and D to SRAM Access Cycle, 288-bit (Table 48.). . . . . . . . 117

Shift of SSF and SSV from SADR (Table 49.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

MIXED SEARCHES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Tables Configured with Different Widths Using an M7040N with CFG_L LOW . . . . . . . . . . . . . . 117

Tables Configured to Different Widths using an M7040N with CFG_L HIGH . . . . . . . . . . . . . . . . 117

Timing Diagram for Mixed SEARCH (One Device) (Figure 88.) . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Multi-Width Configurations Example (Figure 89.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Searches with CFG_L Set HIGH (Table 50.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

LRAM AND LDEV DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

LEARN COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Timing Diagram of LEARN: TLSZ = 00 (Figure 90.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timing Diagram of LEARN: TLSZ = 01 (Except on the Last Device) (Figure 91.). . . . . . . . . .

Timing Diagram of LEARN on Device 7: TLSZ = 01 (Figure 92.) . . . . . . . . . . . . . . . . . . . . . .

Latency of SRAM WRITE Cycle from Second Cycle of LEARN Instruction (Table 51.) . . . . .

. . . 121

. . . 122

. . . 123

5/159

M7040N-066ZA1 Related Products

	M7040N-066ZA1	M7040N-100ZA1	M7040N-083ZA1
Description	SPECIALTY TELECOM CIRCUIT, PBGA388, 35 X 35 MM, 1.27 MM PITCH, PLASTIC, BGA-388	SPECIALTY TELECOM CIRCUIT, PBGA388, 35 X 35 MM, 1.27 MM PITCH, PLASTIC, BGA-388	SPECIALTY TELECOM CIRCUIT, PBGA388, 35 X 35 MM, 1.27 MM PITCH, PLASTIC, BGA-388
Is it Rohs certified?	incompatible	incompatible	incompatible
Maker	STMicroelectronics	STMicroelectronics	STMicroelectronics
Parts packaging code	BGA	BGA	BGA
package instruction	35 X 35 MM, 1.27 MM PITCH, PLASTIC, BGA-388	35 X 35 MM, 1.27 MM PITCH, PLASTIC, BGA-388	35 X 35 MM, 1.27 MM PITCH, PLASTIC, BGA-388
Contacts	388	388	388
Reach Compliance Code	not_compliant	not_compliant	not_compliant
JESD-30 code	S-PBGA-B388	S-PBGA-B388	S-PBGA-B388
JESD-609 code	e0	e0	e0
length	35 mm	35 mm	35 mm
Number of functions	1	1	1
Number of terminals	388	388	388
Maximum operating temperature	70 °C	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA
Encapsulate equivalent code	BGA388,26X26,50	BGA388,26X26,50	BGA388,26X26,50
Package shape	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY
power supply	1.5,2.5/3.3 V	1.65,2.5/3.3 V	1.5,2.5/3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.46 mm	2.46 mm	2.46 mm
Nominal supply voltage	1.5 V	1.65 V	1.5 V
surface mount	YES	YES	YES
Telecom integrated circuit types	TELECOM CIRCUIT	TELECOM CIRCUIT	TELECOM CIRCUIT
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	BALL	BALL	BALL
Terminal pitch	1.27 mm	1.27 mm	1.27 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM
width	35 mm	35 mm	35 mm

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