70V9349L9PF datasheet, PDF - EEWORLD Datasheet

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70V9349L9PF: DescriptionTQFP-100, Tray; Categorystorage storage; File Size350KB，18 Pages; ManufacturerIDT (Integrated Device Technology)

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70V9349L9PF Overview

TQFP-100, Tray

70V9349L9PF Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	TQFP
package instruction	14 X 14 MM, 1.4 MM HEIGHT, TQFP-100
Contacts	100
Manufacturer packaging code	PN100
Reach Compliance Code	not_compliant
ECCN code	EAR99
Maximum access time	9 ns
Other features	FLOW-THROUGH OR PIPELINED ARCHITECTURE
I/O type	COMMON
JESD-30 code	S-PQFP-G100
JESD-609 code	e0
length	14 mm
memory density	73728 bit
Memory IC Type	DUAL-PORT SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of ports	2
Number of terminals	100
word count	4096 words
character code	4000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	4KX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP100,.63SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum standby current	0.003 A
Minimum standby current	3 V
Maximum slew rate	0.23 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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IDT70V9359/49L

HIGH-SPEED 3.3V 8/4K x 18

SYNCHRONOUS PIPELINED

OBSOLETE PARTS

DUAL-PORT STATIC RAM

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

Features:

◆

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed clock to data access

– Commercial: 6.5/7.5/9ns (max.)

– Industrial: 7.5ns (max.)

Low-power operation

– IDT70V9359/49L

Active: 450mW (typ.)

Standby: 1.5mW (typ.)

Flow-Through or Pipelined output mode on either port via

the

FT/PIPE

pins

Counter enable and reset features

Dual chip enables allow for depth expansion without

additional logic

Functional Block Diagram

/PIPE

I/O

-I/O

17L

I/O

-I/O

S OR

T F

A D

P E

E ND S

T E

L M IG

O M S

S O

B C

O E

R EW

T N

◆

Full synchronous operation on both ports

– 3.5ns setup to clock and 0ns hold on all control, data, and

address inputs

– Data input, address, and control registers

– Fast 6.5ns clock to data out in the Pipelined output mode

– Self-timed write allows fast cycle time

– 10ns cycle time, 100MHz operation in Pipelined output mode

Separate upper-byte and lower-byte controls for

multiplexed bus and bus matching compatibility

LVTTL- compatible, single 3.3V (±0.3V) power supply

Industrial temperature range (–40°C to +85°C) is

available for 83 MHz

Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-

pin Fine Pitch Ball Grid Array (fpBGA) packages

Green parts available, see ordering information

0/1

1b 0b

b a

1a 0a

0a 1a

0b 1b

0/1

/PIPE

I/O

Control

I/O

-I/O

17R

I/O

-I/O

I/O

Control

12L

(1)

CLK

Counter/

Address

Reg.

MEMORY

ARRAY

Counter/

Address

Reg.

12R

(1)

CLK

ADS

CNTEN

CNTRST

ADS

CNTEN

CNTRST

5638 drw 01

NOTE:

1. A

is a NC for IDT70V9349.

MARCH 2018

DSC-5638/6

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