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IDT70V9199L6PF8

Description
Application Specific SRAM, 128KX9, 6.5ns, CMOS, PQFP100
Categorystorage    storage   
File Size178KB,17 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT70V9199L6PF8 Overview

Application Specific SRAM, 128KX9, 6.5ns, CMOS, PQFP100

IDT70V9199L6PF8 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Reach Compliance Codenot_compliant
Maximum access time6.5 ns
Maximum clock frequency (fCLK)100 MHz
I/O typeCOMMON
JESD-30 codeS-PQFP-G100
JESD-609 codee0
memory density1179648 bit
Memory IC TypeAPPLICATION SPECIFIC SRAM
memory width9
Humidity sensitivity level3
Number of ports2
Number of terminals100
word count131072 words
character code128000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize128KX9
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeQFP
Encapsulate equivalent codeQFP100,.63SQ,20
Package shapeSQUARE
Package formFLATPACK
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)240
power supply3.3 V
Certification statusNot Qualified
Maximum standby current0.002 A
Minimum standby current3 V
Maximum slew rate0.28 mA
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature20
HIGH-SPEED 3.3V
128K x9/x8
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
Features:
IDT70V9199/099L
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 6/7.5/9/12ns (max.)
– Industrial: 9ns (max.)
Low-power operation
– IDT70V9199/099L
Active: 500mW (typ.)
Standby: 1.5mW (typ.)
Flow-Through or Pipelined output mode on either port via
the
FT/PIPE
pins
Dual chip enables allow for depth expansion without
additional logic
Counter enable and reset features
Full synchronous operation on both ports
– 3.5ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time, 100MHz operation in Pipelined output mode
LVTTL- compatible, single 3.3V (±0.3V) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Available in a 100-pin Thin Quad Flatpack (TQFP)
Green parts available, see ordering information
Functional Block Diagram
R/W
L
OE
L
CE
0L
CE
1L
R/W
R
OE
R
CE
0R
CE
1R
1
0
0/1
1
0
0/1
FT/PIPE
L
0/1
1
0
0
1
0/1
FT/PIPE
R
I/O
0L
- I/O
8L(1)
I/O
0R
- I/O
8R(1)
I/O
Control
I/O
Control
.
A
16L
A
0L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
NOTE:
1. I/O
0X
- I/O
7X
for IDT70V9099.
A
16R
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A
0R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
4859 drw 01
JANUARY 2006
1
©2006 Integrated Device Technology, Inc.
DSC-4859/4
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