EEWORLDEEWORLDEEWORLD

Part Number

Search

LP24-09-FREQ9-30D1JK

Description
Parallel - Fundamental Quartz Crystal, 15MHz Min, 27MHz Max, ROHS COMPLIANT PACKAGE-2
CategoryPassive components    Crystal/resonator   
File Size92KB,6 Pages
ManufacturerPletronics
Environmental Compliance  
Download Datasheet Parametric View All

LP24-09-FREQ9-30D1JK Overview

Parallel - Fundamental Quartz Crystal, 15MHz Min, 27MHz Max, ROHS COMPLIANT PACKAGE-2

LP24-09-FREQ9-30D1JK Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerPletronics
package instructionROHS COMPLIANT PACKAGE-2
Reach Compliance Codecompliant
Other featuresAT-CUT CRYSTAL; BULK
Ageing5 PPM/YEAR
Crystal/Resonator TypePARALLEL - FUNDAMENTAL
Drive level1000 µW
frequency stability0.001%
frequency tolerance30 ppm
JESD-609 codee3
load capacitance9 pF
Manufacturer's serial numberLP24
Installation featuresTHROUGH HOLE MOUNT
Maximum operating frequency27 MHz
Minimum operating frequency15 MHz
Maximum operating temperature85 °C
Minimum operating temperature-30 °C
physical sizeL10.8XB4.47XH2.5 (mm)/L0.425XB0.176XH0.098 (inch)
Series resistance40 Ω
surface mountNO
Terminal surfaceMatte Tin (Sn)
LP21 / LP24 / LP49 Series
Low Profile Crystal
February 2010
• The Pletronics’ LP49 Series is a low profile
thru-hole crystal
• Bulk packaging
• 3 MHz to 70 MHz
• HC-49/US
• AT Cut Crystal
LP21 0.082 (2.10mm) high
LP24 0.100 (2.50mm) high
LP49 0.140 (3.56mm) high
Pletronics Inc. certifies this device is in accordance with the
RoHS (2002/95/EC) and WEEE (2002/96/EC) directives.
Pletronics Inc. guarantees the device does not contain the following:
Cadmium, Hexavalent Chromium, Lead (<1000 ppm), Mercury, PBB’s, PBDE’s
Weight of the Device: 0.62 grams
Moisture Sensitivity Level: 1 As defined in J-STD-020C
Second Level Interconnect code: e1, e2 or e3
Electrical Specification:
Item
Frequency Range
Calibration Frequency Tolerance
Frequency Stability over OTR
Equivalent Series Resistance
(ESR)
Min
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Drive Level
Shunt Capacitance
Aging per year
Specified Temperature Range
Storage Temperature Range
(C0)
-
-
-5
-40
-55
Max
70
-
-
200
150
120
100
80
70
60
50
40
35
100
80
60
1
7
+5
+85
+125
Unit
MHz
ppm
ppm
Ohms
Ohms
Ohms
Ohms
Ohms
Ohms
Ohms
Ohms
Ohms
Ohms
Ohms
Ohms
Ohms
mW
pF
ppm
o
o
Condition
AT cut
at +25
o
C + 3
o
C
_
see table on page 3 for
available options
LP49
LP49/LP24
LP49/LP24
LP49/LP24
LP49/LP24
LP49/LP24/LP21
LP49/LP24/LP21
LP49/LP24/LP21
LP49/LP24/LP21
LP49/LP24/LP21
LP49/LP24/LP21
LP49/LP24/LP21
LP49/LP24/LP21
3
rd
Overtone
Fundamental
3 MHz to 4 MHz
4 MHz to 5 MHz
5 MHz to 6 MHz
6 MHz to 7 MHz
7 MHz to 9 MHz
9 MHz to 10 MHz
10 MHz to 13 MHz
13 MHz to 15 MHz
15 MHz to 27 MHz
27 MHz to 30 MHz
27 MHz to 32 MHz
32 MHz to 50 MHz
50 MHz to 70 MHz
use 10 µW for testing
Pad to Pad capacitance
at +25
o
C + 3
o
C
_
see table on page 3 for available options
C
C
Product information is current as of publication date. The product conforms
to specifications per the terms of the Pletronics limited warranty. Production
processsing does not necessarily include testing of all parameters.
Copyright © 2010, Pletronics Inc.
In-depth analysis of the seven secrets of LPC1100 low-power design
By Rob Cosaro, NXP Semiconductors The ARM Cortex-M0 core brings the LPC1100's power consumption figures in line with current low-power microcontrollers, but the core is far more efficient than current...
fish001 MCU
Riding on the trend: How the film and television industry launders money
[color=#000][font=宋体, "][size=13px]The best way for enterprises to turn the company's money into their own is to invest in movies and TV. [/size][/font][/color] [color=#000][font=宋体, "][size=13px]1: T...
兰博 Talking
Systemverilog Downloads
FPGA verification has always been neglected. Usually after RTL simulation, SignalTap and Chipscope are used to solve verification problems. When the FPGA scale becomes larger, the compilation time is ...
洁白如煤 FPGA/CPLD
How to accurately obtain the local sound card device name (device name) or device object pointer
I want to send a packet to the real sound card through the driver at the bottom layer to let it read or write (play/record), ///...Get the sound card device///...Generate irp NTSTATUS status = IoCallD...
diedong123 Embedded System
MIL-STD-1553B introductory video tutorial 1553B bus data courseware
MIL-STD-1553B introductory video tutorial 1553B bus data coursewareThe introductory video tutorial of MIL-STD-1553B introduces in detail the historical background, advantages and applications of the M...
zhhk FPGA/CPLD
What a failure! I couldn't even find the detailed pin description of STM32F103VG.
I'm drawing a board, but I can't find the pinout for the STM32F103VG.Can anyone send me a copy? Thanks.Please don't tell me to download it from the ST website. I've looked for it, but it's not there....
zhufeiyu830 stm32/stm8

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1800  987  2482  2068  1556  37  20  50  42  32 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号