D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu r xmu ai s
o
a
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
DS90UR241Q/DS90UR124Q 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer
Chipset
DS90UR241Q
DS90UR124Q
September 4, 2009
5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and
Deserializer Chipset
General Description
The DS90UR241/124 Chipset translates a 24-bit parallel bus
into a fully transparent data/control FPD-Link II LVDS serial
stream with embedded clock information. This chipset is ide-
ally suited for driving graphical data to displays requiring 18-
bit color depth - RGB666 + HS, VS, DE + 3 additional general
purpose data channels. This single serial stream simplifies
transferring a 24-bit bus over PCB traces and cable by elim-
inating the skew problems between parallel data and clock
paths. It saves system cost by narrowing data paths that in
turn reduce PCB layers, cable width, and connector size and
pins.
The DS90UR241/124 incorporates FPD-Link II LVDS signal-
ing on the high-speed I/O. FPD-Link II LVDS provides a low
power and low noise environment for reliably transferring data
over a serial transmission path. By optimizing the Serializer
output edge rate for the operating frequency range EMI is fur-
ther reduced.
In addition, the device features pre-emphasis to boost signals
over longer distances using lossy cables. Internal DC bal-
anced encoding/decoding is used to support AC-Coupled
interconnects. Using National Semiconductor’s proprietary
random lock, the Serializer’s parallel data are randomized to
the Deserializer without the need of REFCLK.
■
24:1 interface compression
■
Embedded clock with DC Balancing supports AC-coupled
■
■
■
■
■
■
■
■
■
■
■
data transmission
Capable to drive up to 10 meters shielded twisted-pair
cable
No reference clock required (deserializer)
Meets ISO 10605 ESD - Greater than 8 kV HBM ESD
structure
Hot plug support
EMI Reduction - Serializer accepts spread spectrum input;
data randomization and shuffling on serial link;
Deserializer provides Adjustable PTO (progressive turn-
on) LVCMOS outputs
@Speed BIST (built-in self test) to validate LVDS
transmission path
Individual power-down controls for both Transmitter and
Receiver
Power supply range 3.3V ± 10%
48-pin TQFP package for Transmitter and 64-pin TQFP
package for Receiver
Temperature range -40°C to +105°C
Backward compatible mode with DS90C241/DS90C124
Features
■
Supports displays with 18-bit color depth
■
5MHz to 43MHz pixel clock
■
Automotive grade product AEC-Q100 grade 2 qualified
Applications
■
■
■
■
Automotive Central Information Display
Automotive Instrument Cluster Display
Automotive Heads-Up Display
Remote Camera-based Driver Assistance Systems
Applications Diagram
20194527
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
© 2009 National Semiconductor Corporation
201945
www.national.com
DS90UR241Q/DS90UR124Q
Block Diagram
20194501
Ordering Information
NSID
DS90UR241QVS
DS90UR241QVSX
DS90UR241IVS
DS90UR241IVSX
DS90UR124QVS
DS90UR124QVSX
DS90UR124IVS
DS90UR124IVSX
Package Type
48-Lead TQFP style, 7.0 X 7.0 X 1.0 mm, 0.5 mm pitch
48-Lead TQFP style, 7.0 X 7.0 X 1.0 mm, 0.5 mm pitch
48-Lead TQFP style, 7.0 X 7.0 X 1.0 mm, 0.5 mm pitch
48-Lead TQFP style, 7.0 X 7.0 X 1.0 mm, 0.5 mm pitch
64-Lead TQFP style, 10.0 X 10.0 X 1.0 mm, 0.5 mm pitch
64-Lead TQFP style, 10.0 X 10.0 X 1.0 mm, 0.5 mm pitch
64-Lead TQFP style, 10.0 X 10.0 X 1.0 mm, 0.5 mm pitch
64-Lead TQFP style, 10.0 X 10.0 X 1.0 mm, 0.5 mm pitch
Package ID
VBC48A
VBC48A
VBC48A
VBC48A
VEC64A
VEC64A
VEC64A
VEC64A
1000
1000
1000
1000
Quantity
www.national.com
2
DS90UR241Q/DS90UR124Q
Absolute Maximum Ratings
(Note
1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
DD
)
−0.3V to +4V
LVCMOS Input Voltage
−0.3V to (V
DD
+0.3V)
LVCMOS Output Voltage
−0.3V to (V
DD
+0.3V)
LVDS Receiver Input Voltage
−0.3V to +3.9V
LVDS Driver Output Voltage
−0.3V to +3.9V
LVDS Output Short Circuit Duration
10 ms
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
Lead Temperature
(Soldering, 4 seconds)
+260°C
Maximum Package Power Dissipation Capacity
(Note
2)
Package De-rating:
1/θ
JA
°C/W above +25°C
DS90UR241 − 48L TQFP
θ
JA
θ
JC
DS90UR124 − 64L TQFP
θ
JA
θ
JC
45.8 (4L*); 75.4 (2L*) °C/W
21.0°C/W
42.8 (4L*); 67.2 (2L*)°C/W
14.6°C/W
ESD Rating (HBM)
ESD Rating (ISO10605)
Contact Discharge (D
OUT+
, D
OUT−
)
Air Discharge (D
OUT+
, D
OUT−
)
Contact Discharge (R
IN+
, R
IN−
)
Air
Discharge (R
IN+
, R
IN−
)
≥
±8 kV
R
D
= 2 kΩ, C
S
= 330 pF
±10 kV
±30 kV
±10 kV
±30 kV
Recommended Operating
Conditions
Supply Voltage (V
DD
)
Operating Free Air
Temperature (T
A
)
Clock Rate
Supply Noise
Min
3.0
−40
5
Nom
3.3
+25
Max
3.6
+105
43
±100
Units
V
°C
MHz
mV
P-P
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
V
IH
V
IL
V
CL
Parameter
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
I
CL
= −18 mA
Conditions
Pin/Freq.
Min
Typ
Max
V
DD
0.8
Units
V
V
LVCMOS DC SPECIFICATIONS
Tx:
D
IN
[0:23], TCLK,
2.0
TPWDNB, DEN, TRFB, GND
RAOFF, VODSEL,
RES0.
Rx:
RPWDNB, RRFB,
−0.8
REN, PTOSEL,
BISTEN, BISTM,
SLEW, RES0.
Tx:
D
IN
[0:23], TCLK,
TPWDNB, DEN, TRFB,
RAOFF, RES0.
−10
Rx:
RRFB, REN,
PTOSEL, BISTEN,
BISTM, SLEW, RES0.
Rx:
RPWDNB
V
OH
V
OL
I
OS
I
OZ
High Level Output Voltage
Low Level Output Voltage
Output Short Circuit Current
TRI-STATE
®
Output Current
I
OH
= −2 mA, SLEW = L
I
OH
= −4 mA, SLEW = H
I
OL
= +2 mA, SLEW = L
I
OL
= +4 mA, SLEW = H
V
OUT
= 0V
RPWDNB, REN = 0V,
V
OUT
= 0V or V
DD
Rx:
R
OUT
[0:23], RCLK,
LOCK, PASS.
Rx:
R
OUT
[0:23], RCLK,
LOCK, PASS.
−20
2.3
−1.5
V
I
IN
Input Current
V
IN
= 0V or 3.6V
±2
+10
µA
±5
3.0
+20
V
DD
0.5
−110
+30
µA
V
V
mA
µA
GND 0.33
−40
−30
−70
±0.4
3
www.national.com
DS90UR241Q/DS90UR124Q
Symbol
V
TH
V
TL
I
IN
V
OD
ΔV
OD
V
OS
ΔV
OS
I
OS
I
OZ
Parameter
Differential Threshold High
Voltage
Differential Threshold Low
Voltage
Input Current
Output Differential Voltage
(D
OUT+
)–(D
OUT−
)
Output Differential Voltage
Unbalance
Offset Voltage
Offset Voltage Unbalance
Output Short Circuit Current
TRI-STATE Output Current
V
CM
= +1.8V
Conditions
Pin/Freq.
Rx:
R
IN+
, R
IN−
Min
Typ
Max
Units
LVDS DC SPECIFICATIONS
+50
−50
V
IN
= +2.4V, V
DD
= 3.6V
V
IN
= 0V, V
DD
= 3.6V
R
L
= 100Ω,
w/o pre-
emphasis
(Figure
10)
R
L
= 100Ω,
w/o pre-emphasis
R
L
= 100Ω,
w/o pre-emphasis
R
L
= 100Ω,
w/o pre-emphasis
D
OUT
= 0V, D
IN
= H,
TPWDNB = 2.4V
TPWDNB = 0V,
D
OUT
= 0V OR V
DD
TPWDNB = 2.4V, DEN = 0V
D
OUT
= 0V OR V
DD
TPWDNB = 2.4V, DEN = 2.4V,
D
OUT
= 0V OR V
DD
NO LOCK (NO TCLK)
I
DDT
Serializer
Total Supply Current
(includes load current)
R
L
= 100Ω,
PRE = OFF,
RAOFF = H, VODSEL = L
R
L
= 100Ω,
PRE = 12 kΩ,
RAOFF = H, VODSEL = L
R
L
= 100Ω,
PRE = OFF,
RAOFF = H, VODSEL = H
I
DDTZ
I
DDR
Serializer
Supply Current Power-down
Deserializer
Total Supply Current
(includes load current)
TPWDNB = 0V
(All other LVCMOS Inputs = 0V)
C
L
= 4 pF,
SLEW = H
f = 43 MHz,
CHECKER BOARD
Pattern LVCMOS
Output
(Figure
2)
f = 43 MHz,
RANDOM pattern
LVCMOS Output
f = 43 MHz,
CHECKER BOARD
Pattern
(Figure
1)
VODSEL = L
Tx:
D
OUT+
, D
OUT−
VODSEL = H
VODSEL = L
VODSEL = H
VODSEL = L
VODSEL = H
VODSEL = L
VODSEL = H
VODSEL = L
VODSEL = H
380
500
±100
±100
500
900
1
1.00 1.25
3
−2.0 −5.0
−4.5 −7.9
−15
−15
±1
±1
±250
±250
630
1100
50
1.50
50
−8.0
−14.0
+15
+15
mV
mV
µA
µA
mV
mV
V
mV
mA
µA
µA
−15
±1
+15
µA
SER/DES SUPPLY CURRENT (DVDD*, PVDD* AND AVDD* PINS)
*DIGITAL, PLL, AND ANALOG VDDS
60
65
f = 43 MHz,
RANDOM pattern
66
85
90
90
45
mA
mA
mA
µA
85
105
mA
C
L
= 4 pF,
SLEW = H
I
DDRZ
Deserializer
Supply Current Power-down
RPWDNB = 0V
(All other LVCMOS Inputs = 0V,
R
IN+
/R
IN-
= 0V)
80
100
mA
50
µA
www.national.com
4
PCB Design
京公网安备 11010802033920号
EEWORLD
