0
R
XCR3032XL 32 Macrocell CPLD
0
14
DS023 (v1.5) January 8, 2002
Preliminary Product Specification
Features
•
•
•
•
•
Lowest power 32 macrocell CPLD
5.0 ns pin-to-pin logic delays
System frequencies up to 200 MHz
32 macrocells with 750 usable gates
Available in small footprint packages
- 48-ball CS BGA (36 user I/O pins)
- 44-pin VQFP (36 user I/O)
- 44-pin PLCC (36 user I/O)
Optimized for 3.3V systems
- Ultra-low power operation
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM
process
- Fast Zero Power™ (FZP) CMOS design
technology
Advanced system features
- In-system programming
- Input registers
- Predictable timing model
- Up to 23 available clocks per function block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clocks
- Eight product term control terms per function block
Fast ISP programming times
Port Enable pin for dual function of JTAG ISP pins
2.7V to 3.6V supply voltage at industrial temperature
range
Programmable slew rate control per macrocell
Security bit prevents unauthorized access
Refer to XPLA3 family data sheet (DS012) for
architecture description
Description
The XCR3032XL is a 3.3V, 32-macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic solutions. A total of two function blocks provide
750 usable gates. Pin-to-pin propagation delays are 5.0 ns
with a maximum system frequency of 200 MHz.
TotalCMOS Design Technique for Fast
Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate imple-
mentation allows Xilinx to offer CPLDs that are both high
performance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
Figure 1
and
Table 1
showing the I
CC
vs. Frequency of our
XCR3032XL TotalCMOS CPLD (data taken with two
resetable up/down, 16-bit counters at 3.3V, 25°C).
20
•
•
Typical I
CC
(mA)
15
10
•
•
•
•
•
•
5
0
0
20
40
60
80
100
120
140
160
180
200
Frequency (MHz)
DS023_01_080101
Figure 1:
I
CC
vs. Frequency at V
CC
= 3.3V, 25°C
Table 1:
I
CC
vs. Frequency
(V
CC
= 3.3V, 25°C)
Frequency (MHz)
Typical I
CC
(mA)
0
0.02
1
0.13
5
0.54
10
1.06
20
2.09
50
5.2
100
10.26
200
20.3
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS023 (v1.5) January 8, 2002
Preliminary Product Specification
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1
XCR3032XL 32 Macrocell CPLD
R
DC Electrical Characteristics Over Recommended Operating Conditions
(1)
Symbol
V
OH(2)
Parameter
Output High voltage
Test Conditions
V
CC
= 3.0V to 3.6V, I
OH
= –8 mA
V
CC
= 2.7V to 3.0V, I
OH
= –8 mA
I
OH
= –500
µA
V
OL
I
IL(4)
I
IH(4)
I
CCSB
I
CC
C
IN
C
CLK
C
I/O
Output Low voltage
Input leakage current
I/O High-Z leakage current
Standby current
Dynamic current
(5,6)
Input pin capacitance
(7)
Clock input capacitance
(7)
I/O pin capacitance
(7)
I
OL
= 8 mA
V
IN
= GND or V
CC
V
IN
= GND or V
CC
V
CC
= 3.6V
f = 1 MHz
f = 50 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
Min.
2.4
2.0
(3)
90% V
CC
-
–10
–10
-
-
-
-
-
-
Max.
-
-
-
0.4
10
10
100
0.25
7.5
8
12
10
Unit
V
V
V
V
µA
µA
µA
mA
mA
pF
pF
pF
Notes:
1. See XPLA3 family data sheet (
DS012
) for recommended operating conditions
2. See
Figure 2
for output drive characteristics of the XPLA3 family.
3. This parameter guaranteed by design and characterization, not by testing.
4. Typical leakage current is less than 1
µA.
5. See
Table 1, Figure 1
for typical values.
6. This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and
unloaded. Inputs are tied to V
CC
or ground. This parameter guaranteed by design and characterization, not testing.
7. Typical values, not tested.
100
90
80
70
60
I
OL
(3.3V)
mA
50
40
30
20
10
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
I
OH
(2.7V)
I
OH
(3.3V)
Volts
DS012_10_041901
Figure 2:
Typical I/V Curve for the XPLA3 Family
2
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1-800-255-7778
DS023 (v1.5) January 8, 2002
Preliminary Product Specification
R
XCR3032XL 32 Macrocell CPLD
AC Electrical Characteristics Over Recommended Operating Conditions
(1,2)
-5
Symbol
T
PD1
T
PD2
T
CO
T
SUF
T
SU1(4)
T
SU2
T
H(4)
T
WLH(4)
T
PLH(4)
T
R(4)
T
L(4)
f
SYSTEM(4)
T
CONFIG(4)
T
INIT(4)
T
POE(4)
T
POD(4)
T
PCO(4)
T
PAO (4)
Parameter
Propagation delay time (single p-term)
Propagation delay time (OR array)
(3)
Clock to output (global synchronous pin clock)
Setup time (fast input register)
Setup time (single p-term)
Setup time (OR array)
Hold time
Global Clock pulse width (High or Low)
P-term clock pulse width
Input rise time
Input fall time
Maximum system frequency
Configuration time
(5)
ISP initialization time
P-term OE to output enabled
P-term OE to output disabled
(6)
P-term clock to output
P-term set/reset to output valid
2.5
3.0
3.5
0
2.5
4.0
-
-
-
-
-
-
-
-
-
Min.
Max.
4.5
5.0
3.5
-
-
-
-
-
-
20
20
200
30
30
7.2
7.2
5.5
6.5
3.0
4.3
4.8
0
3.0
5.0
-
-
-
-
-
-
-
-
-
Min.
-
-
-7
Max.
7.0
7.5
5.0
-
-
-
-
-
-
20
20
119
30
30
9.3
9.3
8.3
9.3
Min.
-
-
-
3.0
5.4
6.3
0
4.0
6.0
-
-
-
-
-
-
-
-
-
-10
Max.
9.1
10.0
6.5
-
-
-
-
-
-
20
20
95
30
30
11.2
11.2
10.7
11.2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
µs
µs
ns
ns
ns
ns
Notes:
1. Specifications measured with one output switching.
2. See XPLA3 family data sheet (
DS012
) for recommended operating conditions.
3. See
Figure 4
for derating.
4. These parameters guaranteed by design and/or characterization, not testing.
5. Typical current draw during configuration is 3 mA at 3.6V.
6. Output C
L
= 5 pF.
DS023 (v1.5) January 8, 2002
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
3
XCR3032XL 32 Macrocell CPLD
R
Internal Timing Parameters
(1,2)
-5
Symbol
Buffer Delays
T
IN
T
FIN
T
GCK
T
OUT
T
EN
Input buffer delay
Fast Input buffer delay
Global Clock buffer delay
Output buffer delay
Output buffer enable/disable delay
-
-
-
-
-
0.7
2.2
0.7
1.8
4.5
-
-
-
-
-
1.6
3.0
1.0
2.7
5.0
-
-
-
-
-
2.2
3.1
1.3
3.6
5.7
ns
ns
ns
ns
ns
Parameter
Min.
Max.
Min.
-7
Max.
Min.
-10
Max.
Unit
Internal Register and Combinatorial Delays
T
LDI
T
SUI
T
HI
T
ECSU
T
ECHO
T
COI
T
AOI
T
RAI
T
LOGI1
T
LOGI2
Latch transparent delay
Register setup time
Register hold time
Register clock enable setup time
Register clock enable hold time
Register clock to output delay
Register async. S/R to output delay
Register async. recovery
Internal logic delay (single p-term)
Internal logic delay (PLA OR term)
-
1.0
0.3
2.0
3.0
-
-
-
-
-
1.3
-
-
-
-
1.0
2.0
3.5
2.0
2.5
-
1.0
0.5
2.5
4.5
-
-
-
-
-
1.6
-
-
-
-
1.3
2.3
5.0
2.7
3.2
-
1.2
0.7
3.0
5.5
-
-
-
-
-
2.0
-
-
-
-
1.6
2.1
6.0
3.3
4.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Feedback Delays
T
F
ZIA delay
-
0.5
-
2.9
-
3.5
ns
Time Adders
T
LOGI3
T
UDA
T
SLEW
Fold-back NAND delay
Universal delay
Slew rate limited delay
-
-
-
2.0
1.2
4.0
-
-
-
2.5
2.0
5.0
-
-
-
3.0
2.5
6.0
ns
ns
ns
Notes:
1. These parameters guaranteed by design and characterization, not testing.
2. See XPLA3 family data sheet (
DS012
) for timing model.
4
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1-800-255-7778
DS023 (v1.5) January 8, 2002
Preliminary Product Specification
R
XCR3032XL 32 Macrocell CPLD
Switching Characteristics
VCC
S1
Component
R1
R2
C1
V
OUT
R2
C1
Values
390Ω
390Ω
35 pF
R1
V
IN
Measurement
T
POE (High)
T
POE (Low)
T
P
S1
Open
Closed
Closed
S2
Closed
Open
Closed
S2
Note:
For T
POD
, C1 = 5 pF. Delay measured at
output level of V
OL
+ 300 mV, V
OH
– 300 mV.
DS023_03_102401
Figure 3:
AC Load Circuit
4.5
+3.0V
90%
4.0
10%
0V
T
PD
(ns)
T
R
3.5
T
L
1.5 ns
1.5 ns
3.0
1
2
4
8
16
Measurements:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
DS023_06_042800
Outputs
DS023_05_061101
Figure 5:
Voltage Waveform
Figure 4:
Derating Curve for T
PD2
DS023 (v1.5) January 8, 2002
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
5
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