CAT93C86
(Die Rev. C)
16K-Bit Microwire Serial EEPROM
FEATURES
I
High speed operation: 3MHz
I
Low power CMOS technology
I
1.8 to 5.5 volt operation
I
Selectable x8 or x16 memory organization
I
Self-timed write cycle with auto-clear
I
Hardware and software write protection
I
Power-up inadvertant write protection
I
Sequential read
I
Program enable (PE) pin
I
1,000,000 Program/erase cycles
I
100 year data retention
H
GEN
FR
ALO
EE
LE
A
D
F
R
E
E
TM
I
Commercial, industrial and automotive
temperature ranges
I
RoHS-compliant packages
DESCRIPTION
The CAT93C86 is a 16K-bit Serial EEPROM memory
device which is configured as either registers of 16 bits
(ORG pin at V
CC
) or 8 bits (ORG pin at GND). Each
register can be written (or read) serially by using the
DI (or DO) pin. The CAT93C86 is manufactured using
Catalyst’s advanced CMOS EEPROM floating gate
technology. The device is designed to endure 1,000,000
program/erase cycles and has a data retention of 100
years. The device is available in 8-pin DIP, 8-pin SOIC
and 8-pad TDFN packages.
PIN CONFIGURATION
DIP Package (L)
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
PE
ORG
GND
FUNCTIONAL SYMBOL
SOIC Package (W)
PE
1
2
3
4
8
7
6
5
ORG
GND
DO
DI
V
CC
VCC
CS
SK
ORG
CS
SK
PE
DI
DO
SOIC Package (V)
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
PE
ORG
GND
CS
SK
DI
DO
SOIC Package (X)
1
2
3
4
8
7
6
5
VCC
PE
ORG
GND
GND
PIN FUNCTIONS
Pin Name
CS
Function
Chip Select
Clock Input
Serial Data Input
Serial Data Output
Power Supply
Ground
Memory Organization
Program Enable
TDFN Package (ZD4)
CS
SK
DI
DO
1
2
3
4
8
7
6
5
SK
DI
VCC
PE
ORG
GND
DO
V
CC
GND
ORG
Top View
PE
For Ordering Information details, see page 12.
Note: When the ORG pin is connected to VCC, the x16 organiza-
tion is selected. When it is connected to ground, the x8 pin is
selected. If the ORG pin is left unconnected, then an internal pullup
device will select the x16 organization.
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice.
Doc. No. 1091, Rev. O
CAT93C86
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .................. -55°C to +125°C
Storage Temperature ........................ -65°C to +150°C
Voltage on any Pin with
Respect to Ground
(1)
............. -2.0V to +V
CC
+2.0V
V
CC
with Respect to Ground ................ -2.0V to +7.0V
Package Power Dissipation
Capability (T
A
= 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Typ
Max
Units
Cycles/Byte
Years
Volts
mA
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +5.5V, unless otherwise specified.
Symbol
I
CC1
I
CC2
I
SB1
I
SB2
I
LI
I
LO
V
IL1
V
IH1
V
IL2
V
IH2
V
OL1
V
OH1
V
OL2
V
OH2
Parameter
Power Supply Current
(Write)
Power Supply Current
(Read)
Power Supply Current
(Standby) (x8 Mode)
Power Supply Current
(Standby) (x16Mode)
Input Leakage Current
Output Leakage Current
(Including ORG pin)
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Test Conditions
f
SK
= 1MHz
V
CC
= 5.0V
f
SK
= 1MHz
V
CC
= 5.0V
CS = 0V
ORG=GND
CS=0V
ORG=Float or V
CC
V
IN
= 0V to V
CC
V
OUT
= 0V to V
CC
,
CS = 0V
4.5V
≤
V
CC
< 5.5V
4.5V
≤
V
CC
< 5.5V
1.8V
≤
V
CC
< 4.5V
1.8V
≤
V
CC
< 4.5V
4.5V
≤
V
CC
< 5.5V
I
OL
= 2.1mA
4.5V
≤
V
CC
< 5.5V
I
OH
= -400µA
1.8V
≤
V
CC
< 4.5V
I
OL
= 1mA
1.8V
≤
V
CC
< 4.5V
I
OH
= -100µA
V
CC
- 0.2
2.4
0.2
-0.1
2
0
V
CC
x 0.7
0
Min
Typ
Max
3
500
10
10
1
1
0.8
V
CC
+ 1
V
CC
x 0.2
V
CC
+1
0.4
Units
mA
µA
µA
µA
µA
µA
V
V
V
V
V
V
V
V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
Doc. No. 1091, Rev. O
2
CAT93C86
POWER-UP TIMING
(1)(2)
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max
1
1
Units
ms
ms
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
≤
50ns
0.4V to 2.4V
0.8V, 2.0V
0.2V
CC
to 0.7V
CC
0.5V
CC
4.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
4.5V
1.8V
≤
V
CC
≤
4.5V
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
(3) The input levels and timing reference points are shown in “AC Test Conditions” table.
DEVICE OPERATION
The CAT93C86 is a 16,384-bit nonvolatile memory
intended for use with industry standard microproces-
sors. The CAT93C86 can be organized as either regis-
ters of 16 bits or 8 bits. When organized as X16, seven
13-bit instructions control the reading, writing and erase
operations of the device. When organized as X8, seven
14-bit instructions control the reading, writing and erase
operations of the device. The CAT93C86 operates on
a single power supply and will generate on chip, the high
voltage required during any write operation.
Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin is normally in a high impedance state except when
reading data from the device, or when checking the
ready/busy status after a write operation.
The ready/busy status can be determined after the start
of a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state during chip select by shifting a dummy “1” into the
DI pin. The DO pin will enter the high impedance state on
the falling edge of the clock (SK). Placing the DO pin into
the high impedance state is recommended in applica-
tions where the DI pin and the DO pin are to be tied
together to form a common DI/O pin.
The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 10-bit
address (an additional bit when organized X8) and for
write operations a 16-bit data field (8-bit for X8
organizations).
Enabled mode. For Write Enable and Write Disable
instruction PE=don’t care.
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C86 will
come out of the high impedance state and, after sending
an initial dummy zero bit, will begin shifting out the data
addressed (MSB first). The output data bits will toggle on
the rising edge of the SK clock and are stable after the
specified time delay (t
PD0
or t
PD1
).
After the initial data word has been shifted out and CS
remains asserted with the SK clock continuing to toggle,
the device will automatically increment to the next address
and shift out the next data word in a sequential READ
mode. As long as CS is continuously asserted and SK
continues to toggle, the device will keep incrementing to
the next address automatically until it reaches to the end
of the address space, then loops back to address 0. In
the sequential READ mode, only the initial data word is
preceeded by a dummy zero bit. All subsequent data
words will follow without a dummy zero bit.
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of t
CSMIN
. The falling edge of CS will start the
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C86 can be determined by selecting the device
and polling the DO pin. Since this device features Auto-
Clear before write, it is NOT necessary to erase a
memory location before it is written into.
Note: The Write, Erase, Write all and Erase all instructions
require PE=1. If PE is left floating, 93C86 is in Program
Doc. No. 1091, Rev. O
4
FPGA/CPLD
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