Am29LV400B
4 Megabit (512 K x 8-Bit/256 K x 16-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
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Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Regulated voltage range: 3.0 to 3.6 volt read and
write operations for compatibility with high
performance 3.3 volt microprocessors
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Manufactured on 0.32 µm process technology
— Compatible with 0.5 µm Am29LV400 device
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High performance
— Full voltage range: access times as fast as 70 ns
— Regulated voltage range: access times as fast as
55 ns
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Ultra low power consumption (typical values at
5 MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 7 mA read current
— 15 mA program/erase current
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Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
seven 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
seven 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to prevent
any program or erase operations within that sector
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
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Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
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Top or bottom boot block configurations
available
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Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
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Minimum 1,000,000 write cycle guarantee per sector
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20-year data retention at 125°C
— Reliable operation for the life of the system
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Package option
— 48-ball FBGA
— 48-pin TSOP
— 44-pin SO
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Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
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Data# Polling and toggle bits
— Provides a software method of detecting program
or erase operation completion
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Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
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Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
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Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
21523
Rev:
C
Amendment/+1
Issue Date:
July 2, 1999
GENERAL DESCRIPTION
The Am29LV400B is a 4 Mbit, 3.0 volt-only Flash
memory organized as 524,288 bytes or 262,144 words.
The device is offered in 48-ball FBGA, 44-pin SO, and
48-pin TSOP packages. The word-wide data (x16)
appears on DQ15–DQ0; the byte-wide (x8) data
appears on DQ7–DQ0. This device is designed to be
programmed in-system using only a single 3.0 volt V
CC
supply. No V
PP
is required for write or erase opera-
tions. The device can also be programmed in standard
EPROM programmers.
This device is manufactured using AMD’s 0.32 µm
process technology, and offers all the features and ben-
efits of the Am29LV400, which was manufactured using
0 . 5 µ m pr o c e s s te c h n o l o gy. In a d di t i o n , t h e
Am29LV400B features unlock bypass programming
and in-system sector protection/unprotection.
The standard device offers access times of 55, 70, 90
and 120 ns, allowing high speed microprocessors to
operate without wait states. To eliminate bus contention
the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a
single 3.0 volt power
supply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The
Unlock Bypass
mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the eras e
command sequence. This initiates the
Embedded
Erase
algorithm—an internal algorithm that automatically
pre-programs the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle)
status bits.
After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of
memory. This can be achieved in-system or via pro-
gramming equipment.
The
Erase Suspend
feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby
mode.
Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector simul-
taneously via Fowler-Nordheim tunneling. The data is
programmed using hot electron injection.
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Am29LV400B
51mcu
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