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74LVC373A
Octal D-type transparent latch with 5 V tolerant
inputs/outputs; 3-state
Rev. 3 — 22 November 2012
Product data sheet
1. General description
The 74LVC373A consists of eight D-type transparent latches, featuring separate D-type
inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable
input (pin LE) and an output enable input (pin OE) are common to all internal latches.
When pin LE is HIGH, data at the D-inputs (pins D0 to D7) enters the latches. In this
condition, the latches are transparent, that is, a latch output will change each time its
corresponding D-input changes. When pin LE is LOW, the latches store the information
that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of
pin LE.
When pin OE is LOW, the contents of the eight latches are available at the Q-outputs (pins
Q0 to Q7). When pin OE is HIGH, the outputs go to the high-impedance OFF-state.
Operation of input pin OE does not affect the state of the latches.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices as translators in
mixed 3.3 V and 5 V applications.
The 74LVC373A is functionally identical to the 74LVC573A, but has a different pin
arrangement.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
High-impedance outputs when V
CC
= 0 V
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74LVC373A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC373AD
74LVC373ADB
40 C
to +125
C
40 C
to +125
C
Name
SO20
SSOP20
TSSOP20
Description
Version
plastic small outline package; 20 leads; body width 7.5 SOT163-1
mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT339-1
SOT360-1
SOT764-1
Type number
74LVC373APW
40 C
to +125
C
74LVC373ABQ
40 C
to +125
C
DHVQFN20 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals; body
2.5
4.5
0.85 mm
4. Functional diagram
1
18
17
14
13
8
7
4
3
D7
D6
D5
D4
D3
D2
D1
D0
LE
11
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
OE
18
mna881
EN
C1
19
16
15
12
9
11
3
4
7
8
1D
2
5
6
9
12
15
16
19
mna880
6
5
2
13
14
17
1
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74LVC373A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 22 November 2012
2 of 19
NXP Semiconductors
74LVC373A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
3
4
7
8
13
14
17
18
D0
D1
D2
D3
D4
D5
D6
D7
LATCH
1 to 8
3-STATE
OUTPUTS
Q0
Q1
Q2
Q3
2
5
6
9
LE
Q4 12
Q5 15
Q6 16
Q7 19
LE
LE
11 LE
1 OE
mna882
D
LE
Q
mna189
Fig 3.
Functional diagram
Fig 4.
Logic diagram for one latch
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
mna883
Fig 5.
Logic diagram
74LVC373A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 22 November 2012
3 of 19
NXP Semiconductors
74LVC373A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
5. Pinning information
5.1 Pinning
terminal 1
index area
Q0
D0
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 LE
001aad090
2
3
4
5
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
LE 11
D1
Q1
Q2
D2
D3
Q3
6
7
8
9
GND 10
GND
(1)
373A
1
OE
373A
GND 10
001aad089
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 6.
Pin configuration for SO20 and (T)SSOP20
Fig 7.
Pin configuration for DHVQFN20
5.2 Pin description
Table 2.
Symbol
OE
LE
D[0:7]
Q[0:7]
GND
V
CC
Pin description
Pin
1
11
3, 4, 7, 8, 13, 14, 17, 18
2, 5, 6, 9, 12, 15, 16, 19
10
20
Description
output enable input (active LOW)
latch enable input (active HIGH)
data input
latch output
ground (0 V)
supply voltage
74LVC373A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 22 November 2012
4 of 19
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