Product Obsolete/Under Obsolescence
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XC9500XV Family
High-Performance CPLD
0
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DS049 (v3.0) June 25, 2007
Product Specification
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Excellent quality and reliability
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20 year data retention
ESD protection exceeding 2,000V
Note: This product is being discontinued.
You cannot
order parts in this family after May 14, 2008. Xilinx recom-
mends replacing XC9500XV devices with equivalent
XC9500XL devices in all designs as soon as possible. Rec-
ommended replacements are pin compatible, however
require a V
CC
change to 3.3V, and a recompile of the design
file. In addition, there is no 1.8V I/O support, and for the 144
and 288 macrocell devices only one output bank is sup-
ported. See
XCN07010
for details regarding this discontinu-
ation, including device replacement recomendations for the
XC9500XV device family.
Pin-compatible with 3.3V core XC9500XL family in
common package footprints
Hot Plugging capability
Family Overview
The XC9500XV family is a 2.5V CPLD family targeted for
high-performance, low-voltage applications in leading-edge
communications and computing systems, where high
device reliability and low power dissipation is important.
Each XC9500XV device supports in-system programming
(ISP) and the full IEEE 1149.1 (JTAG) boundary-scan,
allowing superior debug and design iteration capability for
small form-factor packages. The XC9500XV family is
designed to work closely with the Xilinx Spartan™-XL and
Virtex™ FPGA families, allowing system designers to parti-
tion logic optimally between fast interface circuitry and
high-density general purpose logic. As shown in
Table 1,
logic density of the XC9500XV devices ranges from 800 to
6400 usable gates with 36 to 288 registers, respectively.
Multiple package options and associated I/O capacity are
shown in
Table 2.
The XC9500XV family members are fully
pin-compatible, allowing easy design migration across mul-
tiple density options in a given package footprint.
The XC9500XV architectural features address the require-
ments of in-system programmability. Enhanced pin-locking
capability avoids costly board rework. In-system program-
ming throughout the full commercial operating range and a
high programming endurance rating provide worry-free
reconfigurations of system field upgrades. Extended data
retention supports longer and more reliable system operat-
ing life.
Advanced system features include output slew rate control
and user-programmable ground pins to help reduce system
noise. Each user pin is compatible with 3.3V and 2.5V
inputs, and the outputs may be configured for 3.3V, 2.5V, or
1.8V operation. The XC9500XV device exhibits symmetric
full 2.5V output voltage swing to allow balanced rise and fall
times.
Features
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Optimized for high-performance 2.5V systems
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5 ns pin-to-pin logic delays
Small footprint packages including VQFPs, TQFPs
and CSPs (Chip Scale Package)
Lower power operation
Multi-voltage operation
FastFLASH technology
In-system programmable
Output banking (XC95144XV, XC95288XV)
Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
Extra wide 54-input Function Blocks
Up to 90 product-terms per macrocell with
individual product-term allocation
Local clock inversion with three global and one
product-term clocks
Individual output enable per output pin with local
inversion
Input hysteresis on all user and boundary-scan pin
inputs
Bus-hold circuitry on all user pin inputs
Full IEEE Standard 1149.1 boundary-scan (JTAG)
support on all devices
36 to 288 macrocells, with 800 to 6400 usable
gates
Advanced system features
Four pin-compatible device densities
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Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Architecture Description
Each XC9500XV device is a subsystem consisting of multi-
ple Function Blocks (FBs) and I/O Blocks (IOBs) fully inter-
connected by the Fast CONNECT II switch matrix. The IOB
© 2006, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS049 (v3.0) June 25, 2007
Product Specification
www.xilinx.com
1
Product Obsolete/Under Obsolescence
R
XC9500XV Family High-Performance CPLD
Table 1:
XC9500XV Device Family
XC9536XV
T
CO
(ns)
f
SYSTEM
(MHz)
Output Banks
3.5
222
1
XC9572XV
3.5
222
1
XC95144XV
3.5
222
2
XC95288XV
3.8
208
4
Table 2:
XC9500XV Packages and User I/O Pins (not including four dedicated JTAG pins)
(1)
XC9536XV
44-pin VQFP
100-pin TQFP
144-pin CSP
144-pin TQFP
208-pin PQFP
256-pin FBGA
280-pin CSP
34
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XC9572XV
34
72
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XC95144XV
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81
117
117
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XC95288XV
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117
168
192
192
1. Some packages available in Pb-free option. See
Xilinx Packaging
for more information.
Function Block
Each Function Block, as shown in
Figure 2
is comprised of
18 independent macrocells, each capable of implementing
a combinatorial or registered function. The FB also receives
global clock, output enable, and set/reset signals. The FB
generates 18 outputs that drive the Fast CONNECT II
switch matrix. These 18 outputs and their corresponding
output enable signals also drive the IOB.
Logic within the FB is implemented using a sum-of-products
representation. Fifty-four inputs provide 108 true and com-
plement signals into the programmable AND-array to form
90 product terms. Any number of these product terms, up to
the 90 available, can be allocated to each macrocell by the
product term allocator.
DS049 (v3.0) June 25, 2007
Product Specification
www.xilinx.com
3
Product Obsolete/Under Obsolescence
XC9500XV Family High-Performance CPLD
R
Macrocell 1
Programmable
AND-Array
From
Fast CONNECT II
Switch Matrix
54
Product
Term
Allocators
18
18
18
To Fast CONNECT II
Switch Matrix
OUT
To I/O Blocks
PTOE
Macrocell 18
1
3
Global Global
Set/Reset Clocks
DS049_02_041400
Figure 2:
XC9500XV Function Block
Macrocell
Each XC9500XV macrocell may be individually configured
for a combinatorial or registered function. The macrocell
and associated FB logic is shown in
Figure 3.
Five direct product terms from the AND-array are available
for use as primary data inputs (to the OR and XOR gates) to
implement combinatorial functions, or as control inputs
including clock, clock enable, set/reset, and output enable.
The product term allocator associated with each macrocell
selects how the five direct terms are used.
The macrocell register can be configured as a D-type or
T-type flip-flop, or it may be bypassed for combinatorial
operation. Each register supports both asynchronous set
and reset operations. During power-up, all user registers
are initialized to the user-defined preload state (default to 0
if unspecified).
4
www.xilinx.com
DS049 (v3.0) June 25, 2007
Product Specification
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