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SY100S331FCTR

Description
IC,FLIP-FLOP,TRIPLE,D TYPE,ECL100,QFL,24PIN,CERAMIC
Categorylogic    logic   
File Size92KB,8 Pages
ManufacturerMicrel ( Microchip )
Websitehttps://www.microchip.com
Download Datasheet Parametric View All

SY100S331FCTR Overview

IC,FLIP-FLOP,TRIPLE,D TYPE,ECL100,QFL,24PIN,CERAMIC

SY100S331FCTR Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMicrel ( Microchip )
package instructionQFF, QFL24,.4SQ
Reach Compliance Codecompliant
JESD-30 codeS-XQFP-F24
JESD-609 codee0
Logic integrated circuit typeD FLIP-FLOP
Maximum Frequency@Nom-Sup800000000 Hz
Number of functions3
Number of terminals24
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialCERAMIC
encapsulated codeQFF
Encapsulate equivalent codeQFL24,.4SQ
Package shapeSQUARE
Package formFLATPACK
method of packingTAPE AND REEL
power supply-4.5 V
Maximum supply current (ICC)80 mA
Prop。Delay @ Nom-Sup0.8 ns
Certification statusNot Qualified
surface mountYES
technologyECL100K
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationQUAD
Trigger typeMASTER-SLAVE
Micrel, Inc.
TRIPLE D
FLIP-FLOP
SY100S331
SY100S331
FEATURES
s
s
s
s
Max. toggle frequency of 800MHz
Differential outputs
I
EE
min. of –80mA
Industry standard 100K ECL levels
DESCRIPTION
The SY100S331 offers three D-type, edge-triggered
master/slave flip-flops with true and complement outputs,
designed for use in high-performance ECL systems. Each
flip-flop is controlled by a common clock (CP
c
), as well as
its own clock pulse (CP
n
). The resultant clock signal
controlling the flip-flop is the logical OR operation of these
two clock signals. Data enters the master when both CP
c
and CP
n
are LOW and enters the slave on the rising edge
of either CP
c
or CP
n
(or both).
Additional control signals include Master Set (MS) and
Master Reset (MR) inputs. Each flip-flop also has its own
Direct Set (SD
n
) and Direct Clear (CD
n
) signals. The MR,
MS, SD
n
and DC
n
signals override the clock signals. The
inputs on this device have 75KΩ pull-down resistors.
s
Extended supply voltage option:
V
EE
= –4.2V to –5.5V
s
Voltage and temperature compensation for improved
noise immunity
s
Internal 75K
input pull-down resistors
s
150% faster than Fairchild
s
40% lower power than Fairchild
s
Function and pinout compatible with Fairchild F100K
s
Available in 24-pin CERPACK and 28-pin PLCC
packages
BLOCK DIAGRAM
CD
2
CP
C
CP
2
D
2
SD
2
CD
1
CP
1
D
1
SD
1
CD
0
CP
0
D
0
SD
0
C
D
CP
D
S
D
Q
2
Q
2
PIN NAMES
Pin
CP
0
– CP
2
CP
c
D
0
– D
2
CD
0
– CD
2
C
D
CP
D
S
D
Q
1
Q
1
SD
n
MR
MS
Q
0
– Q
2
Q
0
– Q
2
C
D
CP
D
S
D
Q
0
Q
0
V
EES
V
CCA
Function
Individual Clock Inputs
Common Clock Input
Data Inputs
Individual Direct Clear Inputs
Individual Direct Set Inputs
Master Reset Input
Master Set Input
Data Outputs
Complementary Data Outputs
V
EE
Substrate
V
CCO
for ECL Outputs
MS MR
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
Rev.: H
Amendment: /0
1
Issue Date: March 2006

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