IS61QDB42M18-200M3 datasheet, PDF

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IS61QDB42M18-200M3: Description2MX18 DDR SRAM, 0.38ns, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165; Categorystorage storage; File Size446KB，28 Pages; ManufacturerIntegrated Silicon Solution ( ISSI )

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IS61QDB42M18-200M3 Overview

2MX18 DDR SRAM, 0.38ns, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165

IS61QDB42M18-200M3 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Integrated Silicon Solution ( ISSI )
Parts packaging code	BGA
package instruction	15 X 17 MM, 1 MM PITCH, FBGA-165
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	0.38 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	200 MHz
I/O type	SEPARATE
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	17 mm
memory density	37748736 bit
Memory IC Type	DDR SRAM
memory width	18
Number of functions	1
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2MX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.5/1.8,1.8 V
Certification status	Not Qualified
Maximum seat height	1.7 mm
Maximum standby current	0.2 A
Minimum standby current	1.7 V
Maximum slew rate	0.5 mA
Maximum supply voltage (Vsup)	1.89 V
Minimum supply voltage (Vsup)	1.71 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15 mm

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36 Mb (1M x 36 & 2M x 18)

QUAD (Burst of 4) Synchronous SRAMs

ISSI

May 2005

Features

• 1M x 36 or 2M x 18.

• On-chip delay-locked loop (DLL) for wide data

valid window.

• Separate read and write ports with concurrent

read and write operations.

• Synchronous pipeline read with late write opera-

tion.

• Double data rate (DDR) interface for read and

write input ports.

• Fixed 4-bit burst for read and write operations.

• Clock stop support.

• Two input clocks (K and K) for address and con-

trol registering at rising edges only.

• Two input clocks (C and C) for data output con-

trol.

• Two echo clocks (CQ and

CQ)

that are delivered

simultaneously with data.

• +1.8V core power supply and 1.5, 1.8V V

DDQ

used with 0.75, 0.9V V

REF

• HSTL input and output levels.

• Registered addresses, write and read controls,

byte writes, data in, and data outputs.

• Full data coherency.

• Boundary scan using limited set of JTAG 1149.1

functions.

• Byte write capability.

• Fine ball grid array (FBGA) package

- 15mm x 17mm body size

- 1mm pitch

- 165-ball (11 x 15) array

• Programmable impedance output drivers via 5x

user-supplied precision resistor.

Description

The 36Mb

IS61QDB41M36

and

IS61QDB42M18

are synchronous, high-perfor-

mance CMOS static random access memory

(SRAM) devices. These SRAMs have separate I/Os,

eliminating the need for high-speed bus turnaround.

The rising edge of K clock initiates the read/write

operation, and all internal operations are self-timed.

Refer to the

Timing Reference Diagram for Truth

Table

on page

for a description of the basic opera-

tions of these

QUAD (Burst of 4)

SRAMs.

Read and write addresses are registered on alter-

nating rising edges of the K clock. Reads and writes

are performed in double data rate. The following are

registered internally on the rising edge of the K

clock:

•

Read/write address

Read enable

Write enable

Byte writes for burst addresses 1 and 3

Data-in for burst addresses 1 and 3

• Byte writes for burst addresses 2 and 4

• Data-in for burst addresses 2 and 4

Byte writes can change with the corresponding data-

in to enable or disable writes on a per-byte basis. An

internal write buffer enables the data-ins to be regis-

tered one cycle after the write address. The first

data-in burst is clocked one cycle later than the write

command signal, and the second burst is timed to

the following rising edge of the K clock. Two full

clock cycles are required to complete a write opera-

tion.

During the burst read operation, the data-outs from

the first and third bursts are updated from output

registers off the second and fourth rising edges of

the C clock (starting 1.5 cycles later). The data-outs

from the second and fourth bursts are updated with

the third and fifth rising edges of the C clock. The K

and K clocks are used to time the data-outs when-

ever the C and C clocks are tied high. Two full clock

cycles are required to complete a read operation

The device is operated with a single +1.8V power

supply and is compatible with HSTL I/O interfaces.

The following are registered on the rising edge of

the K clock:

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

07/09/04

36 Mb (1M x 36 & 2M x 18)

QUAD (Burst of 4) Synchronous SRAMs

ISSI

Block Diagram

D (Data-In)

36 (or 18)

Data

Reg

36 (or 18)

Write Driver

Output Select

Write/Read Decode

(or 36)

Output Reg

Address

4 (or 2)

Control

Logic

1M x 36

(2M x 18)

Memory

Array

Sense Amps

(or 36)

Output Driver

19 (or 20)

Add

Reg

19 (or 20)

36 (or 18)

Q (Data-Out)

CQ, CQ

(Echo Clock Out)

Clock

Gen

Select Output Control

SRAM Features

Read Operations

The SRAM operates continuously in a burst-of-four mode. Read cycles are started by registering R in active

low state at the rising edge of the K clock. R can be activated every other cycle because two full cycles are

required to complete the burst of four in DDR mode. A second set of clocks, C and C, are used to control the

timing to the outputs. A set of free-running echo clocks, CQ and CQ, are produced internally with timings

identical to the data-outs. The echo clocks can be used as data capture clocks by the receiver device.

When the C and C clocks are connected high, the K and K clocks assume the function of those clocks. In this

case, the data corresponding to the first address is clocked 1.5 cycles later by the rising edge of the K clock.

The data corresponding to the second burst is clocked 2 cycles later by the following rising edge of the K

clock. The third data-out is clocked by the subsequent rising edge of the K clock, and the fourth data-out is

clocked by the subsequent rising edge of the K clock.

A NOP operation (R is high) does not terminate the previous read.

Write Operations

Write operations can also be initiated at every other rising edge of the K clock whenever W is low. The write

address is provided simultaneously. Again, the write always occurs in bursts of four.

The write data is provided in a ‘late write’ mode; that is, the data-in corresponding to the first address of the

burst, is presented 1 cycle later or at the rising edge of the following K clock. The data-in corresponding to the

second write burst address follows next, registered by the rising edge of K. The third data-in is clocked by the

subsequent rising edge of the K clock, and the fourth data-in is clocked by the subsequent rising edge of the

K clock.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

07/09/04

36 Mb (1M x 36 & 2M x 18)

QUAD (Burst of 4) Synchronous SRAMs

ISSI

The data-in provided for writing is initially kept in write buffers. The information in these buffers is written into

the array on the third write cycle. A read cycle to the last two write addresses produces data from the write

buffers. The SRAM maintains data coherency.

During a write, the byte writes independently control which byte of any of the four burst addresses is written

(see

X18/X36 Write Truth Tables

on page

and

Timing Reference Diagram for Truth Table

on page

8).

Whenever a write is disabled (W is high at the rising edge of K), data is not written into the memory.

RQ Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V

to enable the SRAM

to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance

driven by the SRAM. For example, an RQ of 250Ω results in a driver impedance of 50Ω. The allowable range

of RQ to guarantee impedance matching is between 175Ω and 350Ω, with the tolerance described in

Programmable Impedance Output Driver DC Electrical Characteristics

on page 16. The RQ resistor should

be placed less than two inches away from the ZQ ball on the SRAM module. The capacitance of the loaded

ZQ trace must be less than 3 pF.

The ZQ pin can also be directly connected to V

DDQ

to obtain a minimum impedance setting. ZQ must never

be connected to V

Programmable Impedance and Power-Up Requirements

Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by

drifts in supply voltage and temperature. At power-up, the driver impedance is in the middle of allowable

impedances values. The final impedance value is achieved within 1024 clock cycles.

Clock Consideration

This device uses an internal DLL for maximum output data valid window. It can be placed in a stopped-clock

mode to minimize power and requires only 1024 cycles to restart.

No clocks can be issued until V

reaches its allowable operating range.

Single Clock Mode

This device can be also operated in single-clock mode. In this case, C and C are both connected high at

power-up and must never change. Under this condition, K and K will control the output timings.

Either clock pair must have both polarities switching and must never connect to V

REF

, as they are not differ-

ential clocks

Depth Expansion

Separate input and output ports enable easy depth expansion, as each port can be selected and deselected

independently. Read and write operations can occur simultaneously without affecting each other. Also, all

pending read and write transactions are always completed prior to deselecting the corresponding port.

In the following application example, the second pair of C and C clocks is delayed such that the return data

meets the data setup and hold times at the bus master.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

07/09/04

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