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74AUP2G240

Description
Low-power dual inverting buffer/line driver; 3-state
File Size90KB,20 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
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74AUP2G240 Overview

Low-power dual inverting buffer/line driver; 3-state

74AUP2G240
Low-power dual inverting buffer/line driver; 3-state
Rev. 04 — 30 June 2009
Product data sheet
1. General description
The 74AUP2G240 provides the dual inverting buffer/line driver with 3-state output. The
3-state output is controlled by the output enable input (nOE). A HIGH level at pin nOE
causes the output to assume a high-impedance OFF-state.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
This device has the input-disable feature, which allows floating input signals. The inputs
are disabled when the output enable input nOE is HIGH.
2. Features
I
Wide supply voltage range from 0.8 V to 3.6 V
I
High noise immunity
I
Complies with JEDEC standards:
N
JESD8-12 (0.8 V to 1.3 V)
N
JESD8-11 (0.9 V to 1.65 V)
N
JESD8-7 (1.2 V to 1.95 V)
N
JESD8-5 (1.8 V to 2.7 V)
N
JESD8-B (2.7 V to 3.6 V)
I
ESD protection:
N
HBM JESD22-A114E Class 3A exceeds 5000 V
N
MM JESD22-A115-A exceeds 200 V
N
CDM JESD22-C101C exceeds 1000 V
I
Low static power consumption; I
CC
= 0.9
µA
(maximum)
I
Latch-up performance exceeds 100 mA per JESD78 Class II
I
Inputs accept voltages up to 3.6 V
I
Low-noise overshoot and undershoot < 10 % of V
CC
I
Input-disable feature allows floating input conditions
I
I
OFF
circuitry provides partial Power-down mode operation
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C

74AUP2G240 Related Products

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Description Low-power dual inverting buffer/line driver; 3-state Low-power dual inverting buffer/line driver; 3-state Low-power dual inverting buffer/line driver; 3-state Low-power dual inverting buffer/line driver; 3-state Low-power dual inverting buffer/line driver; 3-state
Is it Rohs certified? - conform to - conform to conform to
Maker - NXP - NXP NXP
Parts packaging code - QFN - TSSOP SON
package instruction - VBCC, - VSSOP, VSON,
Contacts - 8 - 8 8
Reach Compliance Code - compliant - compli compli
series - AUP/ULP/V - AUP/ULP/V AUP/ULP/V
JESD-30 code - S-PBCC-B8 - R-PDSO-G8 R-PDSO-N8
length - 1.6 mm - 2.3 mm 1.95 mm
Logic integrated circuit type - BUS DRIVER - BUS DRIVER BUS DRIVER
Humidity sensitivity level - 1 - 1 1
Number of digits - 1 - 1 1
Number of functions - 2 - 2 2
Number of ports - 2 - 2 2
Number of terminals - 8 - 8 8
Maximum operating temperature - 125 °C - 125 °C 125 °C
Minimum operating temperature - -40 °C - -40 °C -40 °C
Output characteristics - 3-STATE - 3-STATE 3-STATE
Output polarity - INVERTED - INVERTED INVERTED
Package body material - PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code - VBCC - VSSOP VSON
Package shape - SQUARE - RECTANGULAR RECTANGULAR
Package form - CHIP CARRIER, VERY THIN PROFILE - SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH SMALL OUTLINE, VERY THIN PROFILE
Peak Reflow Temperature (Celsius) - 260 - 260 260
propagation delay (tpd) - 26.8 ns - 26.8 ns 26.8 ns
Certification status - Not Qualified - Not Qualified Not Qualified
Maximum seat height - 0.5 mm - 1 mm 0.5 mm
Maximum supply voltage (Vsup) - 3.6 V - 3.6 V 3.6 V
Minimum supply voltage (Vsup) - 0.8 V - 0.8 V 0.8 V
Nominal supply voltage (Vsup) - 1.1 V - 1.1 V 1.1 V
surface mount - YES - YES YES
technology - CMOS - CMOS CMOS
Temperature level - AUTOMOTIVE - AUTOMOTIVE AUTOMOTIVE
Terminal form - BUTT - GULL WING NO LEAD
Terminal pitch - 0.5 mm - 0.5 mm 0.5 mm
Terminal location - BOTTOM - DUAL DUAL
Maximum time at peak reflow temperature - 30 - 30 30
width - 1.6 mm - 2 mm 1 mm
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