Data Sheet
June 1999
LG1600KXH Clock and Data Regenerator
Features
s
s
s
s
s
s
s
s
s
s
Integrated clock recovery and data retiming
Surface-mount package
Single ECL supply
Robust FPLL design
Operation up to BER = 1e
–3
SONET/SDH compatible loss of signal alarm
High effective Q allows long run lengths
Jitter tolerance exceeding ITU-T/Bellcore
Low clock jitter generation: <0.005 UI
Standard and custom data rates
0.50 Gbits/s—5.5 Gbits/s
Complementary 50
Ω
I/Os
s
Figure 1. LG1600KXH Open View
Applications
s
SONET/SDH receiver terminals and regenerators
OC-12 through OC-96/STM-4 through STM-32
SONET/SDH test equipment
Proprietary bit rate systems
Digital video transmission
Clock doublers and quadruplers
s
s
s
s
LG1600KXH Clock and Data Regenerator
Data Sheet
June 1999
Regenerated clock and data are available from comple-
mentary outputs that can either be ac coupled, to pro-
vide 50
Ω
output match, or dc coupled with 50
Ω
to
ground at the receiving end.
The second-order PLL filter bandwidth is set by the
user with an external resistor between pin 11 and
ground (required). An internal capacitor provides suffi-
cient PLL damping for most applications. In critical
applications, PLL damping can be increased using an
external capacitor between pins 9 and 11.
The device is powered by a single –5.2 V ECL compat-
ible supply and typically consumes 1.5 W.
The LG1600KXH comes in standard bit rates, but can
be factory tuned for any rate between 500 Mbits/s and
5500 Mbits/s.
A test fixture (TF1004A) with SMA connectors is avail-
able to allow quick evaluation of the LG1600KXH.
Functional Description
The LG1600KXH Clock and Data Regenerator (CDR)
is a compact, single device solution to clock recovery
and data retiming in high-speed communication sys-
tems such as fiber-optic data links and long-span fiber-
optic regenerators and terminals. Using frequency and
phase-lock loop (FPLL) techniques, the device regen-
erates clean clock and error-free data signals from a
nonreturn-to-zero (NRZ) data input, corrupted by jitter
and intersymbol interference. The LG1600KXH
exceeds ITU-T/Bellcore jitter tolerance requirements
for SONET/SDH systems.
The device houses two integrated circuits on an alu-
mina substrate inside a hermetically sealed 3 cm
×
3 cm (1.2 in.
×
1.2 in.) surface-mount package: a GaAs
IC that contains the high-speed part of an FPLL as well
as a highly sensitive decision circuit; and a silicon bipo-
lar IC that contains a loop filter, acquisition, and signal
detect circuitry.
The two ac-coupled complementary data inputs can be
driven differentially as well as single ended. A dc feed-
back voltage V
–FB
maintains a data input threshold
V
–TH
(decision level) that is optimum for a wide range
of 50% duty cycle input levels (connect to V
–TH
). If
needed, the user can supply an external threshold to
compensate for different mark densities or distorted
input signals (see Figure 10).
Theory of Operation
A digital regenerator has the task of retransmitting a bit
stream that is received from a remote source with the
same fidelity at which it was originally transmitted.
Two basic properties of the digital signal need to be
restored: the timing of the transitions between the bits
and the value of each bit.
V
–TH
51
V
–FB
48
V
SS
V
+OUT
43
38
V
–OUT
35
1 kΩ
0.047
µF
50
Ω
0.047
µF
25 kΩ
Q
D
D
31
26
V
–IN
V
+IN
55
60
0.047
µF
V
+CLKO
V
–CLKO
0.047
µF
65
1 kΩ
50
Ω
25 kΩ
0.047
µF
FREQ. &
PHASE
DETECT.
0°
90°
VCO
V
+FB
LOOP CONTROL &
SIGNAL DETECT
0.047
µF
7
V
REF
9
C
EXT
11
R
EXT
LOS
12-3225(F)r.5
Figure 2. LG1600KXH Block Diagram
2
Lucent Technologies Inc.
Data Sheet
June 1999
LG1600KXH Clock and Data Regenerator
Theory of Operation
(continued)
TO FLIP-FLOP
Consequently, the timing information that is present in
the data needs to be extracted and a decision as to the
value of each bit must be made. Both timing instant and
decision levels are critical, since the economics of data
transmission dictate the largest distance possible
between transmitter and receiver. A practically closed
data eye can therefore be expected at the output of the
receiver, allowing only a small decision window.
An added complication in nonreturn-to-zero (NRZ) sys-
tems is the absence of clock component in the data
signal itself. Practical clock recovery circuits have used
a combination of nonlinear processing to extract a
spectral component at the clock frequency and narrow-
band filtering using a SAW filter or dielectric resonator.
The relative bandwidth of such a filter must be on the
order of a few tenths of a percent to minimize the data
pattern dependence of the resulting clock. Temperature
behavior of the passband characteristics, such as
group delay, must be tightly matched to that of the data
path. These extreme requirements make such a dis-
crete design very difficult to manufacture at Gbits/s
data rates.
The LG1600KXH clock and data regenerator relies on
phase-lock loop techniques, rather than passive filter-
ing. The filter properties of a PLL are determined at low
frequencies where parasitic elements play only a minor
roll and stability is easily maintained. Furthermore, the
reference frequency is determined by the data rate
itself, rather than by the physical properties of a band-
pass filter.
Although PLLs can eliminate some of the shortcomings
of passive bandpass filters used in clock recovery cir-
cuits, care was taken in the design of the LG1600KXH
to preserve desired properties such as linearity of the
jitter characteristics. A linear jitter transfer makes it a lot
easier for the system designer to predict the overall
performance of a link.
As a result, the architecture chosen for the device is not
basically different from the conventional clock recovery
circuit. A transition detector extracts a pulse train from
the incoming data signal which is used as a reference
signal for a PLL. The transition pulse train can be seen
as a clock signal that is modulated with the instanta-
neous transition density of the data signal. The PLL
locks onto the frequency and phase of this pulse train
and freewheels during times when transitions are
absent. The LG1600KXH features dual phase detec-
tors; one driven by an in-phase clock which is also driv-
ing the decision circuit flip-flop, the other is driven by a
quadrature clock. The phase detectors produce a zero
output when their respective clocks are centered with
respect to the transition pulses.
Lucent Technologies Inc.
DATA
CIRCULATOR
TRANSITION
PULSE
PDI
0°
FROM
VCO
PDQ
90°
DELAYED
DATA
STUB
LOGIC
FPD OUT
12-3226(F)r.3
Figure 3. Frequency and Phase Detector
For a transition pulse of half the width of the bit period,
the timing diagram of Figure 4 shows how the in-phase
clock ends up in the center of the data eye when the
quadrature-phase detector output is forced to zero by
the loop. The (patented) transition detector is com-
prised of an (active) circulator, a shorted stub, and an
exclusive-OR gate. The circulator/stub combination
produces a delayed version of the data. A transition at
the input of the circuit results in an output pulse from
the exclusive-OR gate whose width equals the return
delay of the stub. The stub is tuned for a given bit rate
and can be adjusted so that the in-phase clock is
exactly centered in the error-free phase range of the
retiming flip-flop.
T
1/2 T
1/4 T
DATA
DELAYED
DATA
TRANSITION
PULSE
0°
CLOCK
90°
CLOCK
12-3227(F)r.2
Figure 4. Timing Diagram
3
LG1600KXH Clock and Data Regenerator
Data Sheet
June 1999
Theory of Operation
(continued)
FPD
OUT
FPD OUT
TIME
A. fck < f
B
–360°
–180°
0°
180°
360°
PHASE
FPD
OUT
TIME
12-3228(C)r.4
Figure 5. Frequency and Phase Detector
Characteristics
The frequency detector is not a separate function but
an integral part of the phase-lock loop. Any transition
between frequency and phase acquisition is completely
avoided. Figure 5 shows the output characteristics of
the FPD, which is essentially an extended range phase
detector. The two quadrature clock phases are used to
produce hysteresis, which extends the phase detector
range to ±270°. The extended range gives the phase
detector a static frequency sensitivity as demonstrated
in Figure 6. For clock frequencies lower than the bit rate
(the phase is increasing), the top trajectory of the dia-
gram in Figure 6 is followed. When the VCO frequency
exceeds the bit rate, the lower trajectory applies. Since
the linear part of the phase detector produces a net-
zero output, in the first instance, positive pulses are fed
into the loop filter increasing the VCO frequency, while
in the latter case, the FPD produces negative pulses.
The wide, 540° range of the phase detector is also
responsible for the high jitter tolerance of the
LG1600KXH and an associated immunity to cycle slip
under high jitter conditions. The clock can be momen-
tarily misaligned as much as 270° but still return to its
original position. This property is extremely important
in synchronous systems, since a cycle slip would cause
misalignment of the demultiplexer following the circuit
resulting in a loss of frame condition. The LG1600KXH
can handle bit error rates up to 1e
–3
as a result of low-
frequency jitter.
B. fck > f
B
12-3229(C)r.3
Figure 6. Frequency Detector Operation
PLL Dimensioning
The LG1600KXH CDR employs a heavily damped
second-order phase-lock loop. A linear model of this
PLL is depicted in Figure 7. The conventional second-
order equation describing the jitter transfer of the PLL
is shown below:
2
ϕ
o
2ςω
n
s
+
ω
n
-
H
(
s
)
=
-----
(
s
)
=
-----------------------------------------
2
2
ϕ
i
s
+
2ςω
n
s
+
ω
n
where
ϕ
i
and
ϕ
o
denote the input and output phase,
respectively,
ς
is the PLL damping ratio and
ω
n
is the
natural frequency. For most clock recovery applications
a very high damping is required that renders the PLL
essentially as a first-order system with a slight peaking
that is generally undesirable. The second-order equa-
tion above does not provide much insight into the peak-
ing and bandwidth parameters.
ϕi
Ko
Kd
C
PHASE DETECTOR
Rx
SUM OF INTERNAL
AND EXTERNAL
LOOP FILTER
CAPACITANCE
VCO
ϕo
12-3230(F)r.4
Figure 7. Phase-Lock Loop Linear Model
4
Lucent Technologies Inc.
Data Sheet
June 1999
LG1600KXH Clock and Data Regenerator
For moderate damping,
ς
> 2.5
(ω
b
τ
< 0.1), the –3 dB
bandwidth of the PLL can be approximated by the loop
gain pole product:
J
BW
≈ ω
b
= K
d
R
x
K
o
while the jitter peaking can be expressed in terms of
the product of PLL bandwidth and loop filter time con-
stant:
1
1
H
(
s
)
max
≈
1
+
--------
=
1
+
------------------------
-
-
2
ω
b
τ
R
x
CK
d
K
o
As the last two expressions make clear, the PLL band-
width is controlled by the value of the external resistor
(see Figure 8), while the peaking depends both on the
resistor value (quadratically) and total loop filter capac-
itance.
Theory of Operation
(continued)
A more useful expression of the PLL characteristics is
the following
*
:
1
ω
b
1
+
-----
sτ
H
(
s
)
=
-------------------------------------
1
s
+
ω
b
1
+
-----
sτ
The jitter transfer is now directly expressed in the phys-
ical loop gain pole product,
ω
b
, and the loop filter time
constant,
τ.
Damping ratio,
ς,
and natural frequency,
ω
n
,
simply relate to these two parameters as follows:
ς
=
0.5
ω
b
τ
ω
n
⁄ τ
and
ω
n
=
* Wolaver, D.H.,
Phase-Locked Loop Circuit Design,
Prentice Hall,
1991.
1.2
3.6
10
°C
1.0
10
°C
0.8
3.0
25
°C
2.4
25
°C
J
BW
(MHz)
J
BW
(MHz)
0.6
70
°C
0.4
1.8
70
°C
1.2
0.2
0.6
0.0
0
50
100
Rx (Ω)
150
200
250
0.0
0
50
100
Rx (Ω)
150
200
250
A. LG1600KXH0622 (Cx = 0.15
µF)
B. LG1600KXH2488 (Cx = 0)
12-3231(F)r.3—12-3232(F)r.3
Figure 8. Jitter Bandwidth vs. External Resistor Value
Lucent Technologies Inc.
5
PCB Design
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