EEWORLDEEWORLDEEWORLD

Part Number

Search

3GPF62GC-30N-FREQ

Description
LVPECL Output Clock Oscillator, 38MHz Min, 640MHz Max, ROHS COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size156KB,1 Pages
ManufacturerEuroquartz
Websitehttp://www.euroquartz.co.uk/
Environmental Compliance  
Download Datasheet Parametric View All

3GPF62GC-30N-FREQ Overview

LVPECL Output Clock Oscillator, 38MHz Min, 640MHz Max, ROHS COMPLIANT, SMD, 6 PIN

3GPF62GC-30N-FREQ Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerEuroquartz
Reach Compliance Codecompliant
Other featuresTRI-STATE; ENABLE/DISABLE FUNCTION
Maximum control voltage2 V
Minimum control voltage1.3 V
maximum descent time0.7 ns
Frequency Adjustment - MechanicalNO
Frequency offset/pull rate30 ppm
frequency stability100%
Installation featuresSURFACE MOUNT
Maximum operating frequency640 MHz
Minimum operating frequency38 MHz
Maximum operating temperature70 °C
Minimum operating temperature
Oscillator typeLVPECL
Output load50 OHM
physical size11.4mm x 9.6mm x 2.5mm
longest rise time0.7 ns
Maximum supply voltage3.465 V
Minimum supply voltage3.135 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
EURO
QUARTZ
11.4 x 9.6 x 2.5mm SMD
Frequency range 38MHz to 640MHz
LVPECL Output
Supply Voltage 3.3 VDC
Phase jitter 0.4ps typical
Pull range from ±30ppm to ±150ppm
DESCRIPTION
GPF62 VCXOs are packaged in a 6 pad 11.4 x 9.6mm SMD package.
Typical phase jitter for GPF series VCXOs is 0.4 ps. Output is LVPECL.
Applications include phase lock loop, SONET/ATM, set-top boxes,
MPEG , audio/video modulation, video game consoles and HDTV.
GPF62 PECL VCXO
38.0MHz to 640.0MHz
OUTLINE & DIMENSIONS
SPECIFICATION
Frequency Range:
Supply Voltage:
Output Logic:
RMS Period Jitter:
Peak to Peak Jitter:
Phase Jitter:
Initial Frequency Accuracy:
Output Voltage HIGH (1):
Output Voltage LOW (0):
Pulling Range:
Control Voltage Range:
Temperature Stability:
Output Load:
Rise/Fall Times:
Duty Cycle:
Start-up Time:
Current Consumption:
Static Discharge Protection:
Storage Temperature:
Ageing:
Enable/Disable:
RoHS Status:
38.0MHz to 640.0MHz
3.3 VDC ±5%
LVPECL
3.0ps typical
20.0ps typical, 30.0ps maximum
0.4ps typical, 5.0ps maximum
Tune to the nominal frequency
with Vc= 1.65 ±0.2VDC
Vdd-1.025V minimum
Vdd-0.880V maximum
Vdd-1.810V minimum
Vdd-1.620V maximum
(RL=50 to Vdd-2V)
From ±30ppm to ±150ppm
1.65 ±0.35 Volts
See table
50W into Vdd or Thevenin equiv.
0.5ns typ., 0.7ns max.
20% Vdd to 80% Vdd
50% ±5%
(Measured at Vdd-1.3V)
10ms maximum, 5ms typical
75mA maximum at 212.5MHz
80mA maximum at 622.08MHz
2kV maximum
-55° to +150°C
±2ppm per year maximum
See table
Fully compliant or non-compliant
FREQUENCY STABILITY
Stability Code Stability ±ppm Temp. Range
A
25
0°~+70°C
B
50
0°~+70°C
C
100
0°~+70°C
D
25
-40°~+85°C
E
50
-40°~+85°C
F
100
-40°~+85°C
If non-standard frequency stability is required
Use ‘I’ followed by stability, i.e. I20 for ±20ppm
ENABLE/DISABLE FUNCTION
Tristate Pad
Status
Not connected
Below 0.3Vdd
(Ref. to ground)
Above 0.7Vdd
(Ref. to ground)
Output Status
LVPECL and Complimentary LVPECL enabled
Both outputs are disabled (high impedance)
Both outputs are enabled
PART NUMBERING
Example:
Supply Voltage
3 = +3.3V
Series Designator
GPF62
RoHS Status
G = Compliant
Blank - Non-compliant
Stability over temperature range
(See table)
Pullability in ±ppm
Pullability determinator
N = minimum
M = maximum
T = Typical
Frequency in MHz
3GPF62GB-80N-60.000
EUROQUARTZ LIMITED Blacknell Lane CREWKERNE Somerset UK TA18 7HE
Tel: +44 (0)1460 230000 Fax: +44 (0)1460 230001 info@euroquartz.co.uk www.euroquartz.co.uk
FPGA ADC Controller
[table=98%] [tr][td]These two wrote a controller program for AD1308 and found that the control signals were normal but there was no output signal in the lower 8 bits after AD conversion. The program i...
rookiefx FPGA/CPLD
Slib_ClearScr()--44b0/2440 clear display buffer function
Slib_ClearScr() { int i,j; for(j=0;j<240;j++) for(i=0;i<10;i++) { frameBuffer1[j][i]=0x00000000; } } ARM clears the display buffer function prototype. Why is for(i=0;i<10;i++) not executed 10 times wh...
jacyko Embedded System
NI Technical Information Super Complete
[i=s]This post was last edited by littleshrimp on 2014-9-27 08:26[/i] [size=5]Some netizens said that [url]http://instruments.testmart.cn/[/url] has a lot of good information[/size].[size=5]But it is ...
littleshrimp Robotics Development
C51 example program for 1-wire communication protocol
C51 example program for 1-wire communication protocol...
wangwei20060608 51mcu
PCB diagram of optical fiber Ethernet card for PCI bus
I drew a PCB diagram of a 100M fiber optic Ethernet card for PCI bus 2 years ago. Anyone interested? I will add the attachment in the evening. [[i] This post was last edited by Simon on 2009-5-12 20:0...
西门 FPGA/CPLD
EEWORLD University Hall----Introduction to TI DLP LightCrafter DLP2000 EVM Board
TI DLP LightCrafter DLP2000 EVM board introduction : https://training.eeworld.com.cn/course/4161...
hi5 Talking

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 354  517  1720  1890  31  8  11  35  39  1 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号