HD74ACT165T-ELL datasheet, PDF

HD74ACT165T-ELL: DescriptionParallel In Serial Out, ACT Series, 8-Bit, Right Direction, Complementary Output, CMOS, PDSO16, TTP-16DA; Categorylogic logic; File Size65KB，11 Pages; ManufacturerHitachi （Renesas ）; Websitehttp://www.renesas.com/eng/

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HD74ACT165T-ELL Overview

Parallel In Serial Out, ACT Series, 8-Bit, Right Direction, Complementary Output, CMOS, PDSO16, TTP-16DA

Parameter Name	Attribute value
Maker	Hitachi （Renesas ）
Parts packaging code	SOIC
package instruction	TSSOP,
Contacts	16
Reach Compliance Code	unknown
Other features	CLOCK INHIBIT
Counting direction	RIGHT
series	ACT
JESD-30 code	R-PDSO-G16
length	5 mm
Logic integrated circuit type	PARALLEL IN SERIAL OUT
Number of digits	8
Number of functions	1
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
propagation delay (tpd)	16.5 ns
Certification status	Not Qualified
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Trigger type	POSITIVE EDGE
width	4.4 mm
minfmax	60 MHz

HD74AC165/HD74ACT165

Parallel-Load 8-bit Shift Register

ADE-205-374 (Z)

1st. Edition

Sep. 2000

Description

This 8-bit serial shift register shifts data from Q

to Q

when clocked, Parallel inputs to each stage are

enabled by a low level at the Shift/Load Input. Also included is a gated clock input and a complementary

output from the eighth bit.

Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock inhibit

function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with

the Shift/Load input high enables the other clock input. Data transfer occurs on the positive going edge of

the clock. Parallel loading is inhibited as long as the Shift/Load input is high. When taken low, data at the

parallel inputs is loaded directly into the register independent of the state of the clock.

Features

•

Outputs Source/Sink 24 mA

•

HD74ACT165 has TTL-Compatible Inputs

	HD74ACT165T-ELL	HD74AC165T-ELL
Description	Parallel In Serial Out, ACT Series, 8-Bit, Right Direction, Complementary Output, CMOS, PDSO16, TTP-16DA	Parallel In Serial Out, AC Series, 8-Bit, Right Direction, Complementary Output, CMOS, PDSO16, TTP-16DA
Maker	Hitachi （Renesas ）	Hitachi （Renesas ）
Parts packaging code	SOIC	SOIC
package instruction	TSSOP,	TSSOP,
Contacts	16	16
Reach Compliance Code	unknown	unknown
Other features	CLOCK INHIBIT	ALSO OPRATES AT 5V VCC NOMINAL; CLOCK INHIBIT
Counting direction	RIGHT	RIGHT
series	ACT	AC
JESD-30 code	R-PDSO-G16	R-PDSO-G16
length	5 mm	5 mm
Logic integrated circuit type	PARALLEL IN SERIAL OUT	PARALLEL IN SERIAL OUT
Number of digits	8	8
Number of functions	1	1
Number of terminals	16	16
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Output polarity	COMPLEMENTARY	COMPLEMENTARY
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TSSOP
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
propagation delay (tpd)	16.5 ns	21.5 ns
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.1 mm	1.1 mm
Maximum supply voltage (Vsup)	5.5 V	3.6 V
Minimum supply voltage (Vsup)	4.5 V	3 V
Nominal supply voltage (Vsup)	5 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm
Terminal location	DUAL	DUAL
Trigger type	POSITIVE EDGE	POSITIVE EDGE
width	4.4 mm	4.4 mm
minfmax	60 MHz	90 MHz

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