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EP20K400GC655-1

Description
Loadable PLD, 2.5ns, CMOS, CPGA655, PGA-655
CategoryProgrammable logic devices    Programmable logic   
File Size1MB,132 Pages
ManufacturerAltera (Intel)
Download Datasheet Parametric View All

EP20K400GC655-1 Overview

Loadable PLD, 2.5ns, CMOS, CPGA655, PGA-655

EP20K400GC655-1 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerAltera (Intel)
Parts packaging codePGA
package instructionPGA, SPGA655,47X47
Contacts655
Reach Compliance Codeunknown
ECCN code3A001.A.7.A
JESD-30 codeS-CPGA-P655
JESD-609 codee0
length62.484 mm
Humidity sensitivity level1
Dedicated input times4
Number of I/O lines502
Number of entries496
Number of logical units16640
Output times496
Number of terminals655
Maximum operating temperature85 °C
Minimum operating temperature
organize4 DEDICATED INPUTS, 502 I/O
Output functionMACROCELL
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codePGA
Encapsulate equivalent codeSPGA655,47X47
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)220
power supply2.5,2.5/3.3 V
Programmable logic typeLOADABLE PLD
propagation delay2.5 ns
Certification statusNot Qualified
Maximum seat height4.08 mm
Maximum supply voltage2.625 V
Minimum supply voltage2.375 V
Nominal supply voltage2.5 V
surface mountNO
technologyCMOS
Temperature levelOTHER
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
Maximum time at peak reflow temperatureNOT SPECIFIED
width62.484 mm
APEX 20K
Programmable Logic
Device Family
March 2004, ver. 5.1
Data Sheet
Features
Industry’s first programmable logic device (PLD) incorporating
system-on-a-programmable-chip (SOPC) integration
MultiCore
TM
architecture integrating look-up table (LUT) logic,
product-term logic, and embedded memory
LUT logic used for register-intensive functions
Embedded system block (ESB) used to implement memory
functions, including first-in first-out (FIFO) buffers, dual-port
RAM, and content-addressable memory (CAM)
ESB implementation of product-term logic used for
combinatorial-intensive functions
High density
30,000 to 1.5 million typical gates (see
Tables 1
and
2)
Up to 51,840 logic elements (LEs)
Up to 442,368 RAM bits that can be used without reducing
available logic
Up to 3,456 product-term-based macrocells
Note (1)
EP20K100
263,000
Table 1. APEX 20K Device Features
Feature
Maximum
system
gates
Typical
gates
LEs
ESBs
Maximum
RAM bits
Maximum
macrocells
Maximum
user I/O
pins
EP20K30E
113,000
EP20K60E
162,000
EP20K100E
263,000
EP20K160E
404,000
EP20K200
526,000
EP20K200E
526,000
30,000
1,200
12
24,576
192
128
60,000
2,560
16
32,768
256
196
100,000
4,160
26
53,248
416
252
100,000
4,160
26
53,248
416
246
160,000
6,400
40
81,920
640
316
200,000
8,320
52
106,496
832
382
200,000
8,320
52
106,496
832
376
Altera Corporation
DS-APEX20K-5.1
1
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