74LVC1G99_10 datasheet, PDF - EEWORLD Datasheet

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74LVC1G99_10: DescriptionUltra-configurable multiple function gate; 3-state; File Size201KB，29 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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74LVC1G99_10 Overview

Ultra-configurable multiple function gate; 3-state

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74LVC1G99

Ultra-configurable multiple function gate; 3-state

Rev. 04 — 16 April 2010

Product data sheet

1. General description

The 74LVC1G99 provides a low voltage, ultra-configurable, multiple function gate with

3-state output. The device can be configured as one of several logic functions including,

AND, OR, NAND, NOR, XOR, XNOR, inverter, buffer and MUX. No external components

are required to configure the device as all inputs can be connected directly to V

GND. The 3-state output is controlled by the output enable input (OE). A HIGH level at OE

causes the output (Y) to assume a high-impedance OFF-state. When OE is LOW, the

output state is determined by the signals applied to the Schmitt-trigger inputs (A, B, C and

D).

Due to the use of Schmitt-trigger inputs the device is tolerant of slowly changing input

signals, transforming them into sharply defined, jitter free output signals. By eliminating

leakage current paths to V

and GND, the inputs and disabled output are also

over-voltage tolerant, making the device suitable for mixed-voltage applications.

This device is fully specified for partial power-down applications using I

OFF

The I

OFF

circuitry disables the output, preventing the damaging backflow current through

the device when it is powered down.

The 74LVC1G99 is fully specified over the supply range from 1.65 V to 5.5 V.

2. Features and benefits

Wide supply voltage range from 1.65 V to 5.5 V

5 V tolerant inputs for interfacing with 5 V logic

High noise immunity

Complies with JEDEC standard:

JESD8-7 (1.65 V to 1.95 V)

JESD8-5 (2.3 V to 2.7 V)

JESD8-B/JESD36 (2.7 V to 3.6 V)

ESD protection:

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

±24

mA output drive (V

= 3.0 V)

CMOS low power consumption

Latch-up performance exceeds 250 mA

Direct interface with TTL levels

Inputs accept voltages up to 5 V

Multiple package options

Specified from

−40 °C

to +85

°C

and

−40 °C

to +125

°C.

74LVC1G99_10 Related Products

	74LVC1G99_10	74LVC1G99GF	74LVC1G99	74LVC1G99GM	74LVC1G99DP	74LVC1G99GD	74LVC1G99GT
Description	Ultra-configurable multiple function gate; 3-state	Ultra-configurable multiple function gate; 3-state	Ultra-configurable multiple function gate; 3-state	Ultra-configurable multiple function gate; 3-state	Ultra-configurable multiple function gate; 3-state	Ultra-configurable multiple function gate; 3-state	Ultra-configurable multiple function gate; 3-state
Is it Rohs certified?	-	conform to	-	conform to	conform to	conform to	conform to
Maker	-	NXP	-	NXP	NXP	NXP	NXP
Parts packaging code	-	SON	-	QFN	SOIC	SON	SON
package instruction	-	1.35 X 1 MM, 0.50 MM HEIGHT, MO-252, SOT-1089, SON-8	-	1.60 X 1.60 MM, 0.50 MM HEIGHT, PLASTIC, MO-255, SOT902-1, QFN-8	3 MM, PLASTIC, SOT505-2, TSSOP-8	3 X 2 MM, 0.50 MM HEIGHT, PLASTIC, SOT996-2, SON-8	1 X 1.95 MM, 0.50 MM HEIGHT, PLASTIC, MO-252, SOT833-1, SON-8
Contacts	-	8	-	8	8	8	8
Reach Compliance Code	-	unknow	-	compli	compli	unknow	compli
series	-	LVC/LCX/Z	-	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z
JESD-30 code	-	R-PDSO-N8	-	S-PQCC-N8	S-PDSO-G8	R-PDSO-N8	R-PDSO-N8
JESD-609 code	-	e3	-	e4	e4	-	e3
length	-	1.35 mm	-	1.6 mm	3 mm	3 mm	1.95 mm
Logic integrated circuit type	-	MAJORITY LOGIC GATE	-	MAJORITY LOGIC GATE	MAJORITY LOGIC GATE	MAJORITY LOGIC GATE	MAJORITY LOGIC GATE
Humidity sensitivity level	-	1	-	1	1	1	1
Number of functions	-	1	-	1	1	1	1
Number of entries	-	4	-	4	4	4	4
Number of terminals	-	8	-	8	8	8	8
Maximum operating temperature	-	125 °C	-	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-	-40 °C	-	-40 °C	-40 °C	-40 °C	-40 °C
Output characteristics	-	3-STATE	-	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	-	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	-	VSON	-	VQCCN	TSSOP	VSON	VSON
Package shape	-	RECTANGULAR	-	SQUARE	SQUARE	RECTANGULAR	RECTANGULAR
Package form	-	SMALL OUTLINE, VERY THIN PROFILE	-	CHIP CARRIER, VERY THIN PROFILE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, VERY THIN PROFILE	SMALL OUTLINE, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	-	260	-	260	260	260	260
propagation delay (tpd)	-	38.5 ns	-	38.5 ns	38.5 ns	38.5 ns	38.5 ns
Certification status	-	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	-	0.5 mm	-	0.5 mm	1.1 mm	0.5 mm	0.5 mm
Maximum supply voltage (Vsup)	-	5.5 V	-	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	-	1.65 V	-	1.65 V	1.65 V	1.65 V	1.65 V
Nominal supply voltage (Vsup)	-	2.3 V	-	2.3 V	2.3 V	2.3 V	2.3 V
surface mount	-	YES	-	YES	YES	YES	YES
technology	-	CMOS	-	CMOS	CMOS	CMOS	CMOS
Temperature level	-	AUTOMOTIVE	-	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
Terminal surface	-	PURE TIN	-	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	-	Tin (Sn)
Terminal form	-	NO LEAD	-	NO LEAD	GULL WING	NO LEAD	NO LEAD
Terminal pitch	-	0.35 mm	-	0.5 mm	0.65 mm	0.5 mm	0.5 mm
Terminal location	-	DUAL	-	QUAD	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	-	30	-	30	30	30	30
width	-	1 mm	-	1.6 mm	3 mm	2 mm	1 mm

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