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74LVC3G34DP

Description
Triple buffer gate
Categorylogic    logic   
File Size79KB,16 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Environmental Compliance
Download Datasheet Parametric Compare View All

74LVC3G34DP Overview

Triple buffer gate

74LVC3G34DP Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerNXP
Parts packaging codeSOIC
package instruction3 MM, PLASTIC, SOT505-2, TSSOP-8
Contacts8
Reach Compliance Codecompliant
seriesLVC/LCX/Z
JESD-30 codeS-PDSO-G8
JESD-609 codee4
length3 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeBUFFER
MaximumI(ol)0.024 A
Humidity sensitivity level1
Number of functions3
Number of entries1
Number of terminals8
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP8,.16
Package shapeSQUARE
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Prop。Delay @ Nom-Sup5.1 ns
propagation delay (tpd)10.8 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height1.1 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)1.65 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceNICKEL PALLADIUM GOLD
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width3 mm
Base Number Matches1
74LVC3G34
Triple buffer
Rev. 07 — 9 May 2008
Product data sheet
1. General description
The 74LVC3G34 provides three buffers.
The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of
the 74LVC3G34 as a translator in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
2. Features
I
I
I
I
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
N
JESD8-7 (1.65 V to 1.95 V)
N
JESD8-5 (2.3 V to 2.7 V)
N
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
±24
mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Multiple package options
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C
I
I
I
I
I
I
I

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