a
FEATURES
Low Cost
Low Transition Noise between Code
12-Bit Accurate
1/2 LSB Nonlinearity Error over Temperature
No Missing Codes at All Temperatures
10 s Conversion Time
Internal or External Clock
8- or 16-Bit Data Bus Compatible
Improved ESD Resistant Design
Latchup Resistant Epi-CMOS Processing
Low 95 mW Power Consumption
Space-Saving 24-Lead 0.3" DIP, or 24-Lead SOIC
APPLICATIONS
Data Acquisition Systems
DSP System Front End
Process Control Systems
Portable Instrumentation
GENERAL DESCRIPTION
CMOS Microprocessor-Compatible
12-Bit A/D Converter
ADC912A
FUNCTIONAL BLOCK DIAGRAM
AGND V
REFIN
5k
12-BIT DAC
A
IN
V
DD
V
SS
ADC912A
SUCCESSIVE
APPROXIMATION
REGISTER
12-BIT LATCH
4
8
CONTROL
LOGIC
BUSY
CS
RD
HBEN
MULTIPLEXER
8
THREE-STATE
OUTPUT
DRIVERS
THREE-STATE
OUTPUT
DRIVERS
CLOCK
OSCILLATOR
CLK OUT
CLK IN
D
11
D
8
D
7
D
4
DGND D
3/11
D
0/8
The ADC912A is a monolithic 12-bit accurate CMOS A/D
converter. It contains a complete successive-approximation A/D
converter built with a high-accuracy D/A converter, a precision
bipolar transistor high-speed comparator, and successive-
approximation logic including three-state bus interface for logic
compatibility. The accuracy of the ADC912A results from the
addition of precision bipolar transistors to Analog Devices’
advanced-oxide isolated silicon-gate CMOS process. Particular
attention was paid to the reduction of transition noise between
adjacent codes achieving a 1/6 LSB uncertainty. The low noise
design produces the same digital output for dc analog inputs
256
not located at a transition voltage, see Figures 1 and 2. NPN
digital output transistors provide excellent bus interface timing,
125 ns access and bus disconnect time which results in faster
data transfer without the need for wait states. An external
1.25 MHz clock provides a 10
µs
conversion time.
In stand-alone applications an internal clock can be used with
external crystal.
An external negative five-volt reference sets the 0 V to 10 V
input range. Plus 5 V and minus 12 V power supplies result in
95 mW of total power consumption.
NUMBER OF OCCURRENCES
192
128
64
DIGITAL OUTPUT
10
0%
256 SUCCESSIVE
CONVERSIONS
WITH
A
IN
= 4.99756V
100
90
TRANSITION NOISE
0
2045 2046 2047 2048 2049
OUTPUT CODE – Decimal
ANALOG INPUT
Figure 1. Code Repetition
Figure 2. Transition Noise Cross Plot
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
(V =
V
ADC912A–SPECIFICATIONS
ADC912A/F+5unless5%, V = –11.4 V to –15.75 V, V
10 V; External f = 1.25 MHz; –40 C to +85 C applies to
otherwise noted.)
DD
SS
CLK
REFIN
= –5 V, Analog Input O V to
Max
+1
+1
+5
+6
15
10
3
Unit
LSB
LSB
LSB
LSB
ppm/°C
V
mA
mA
mA
mW
LSB
LSB
V
V
µA
pF
V
V
µA
pF
Parameter
STATIC ACCURACY
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Full-Scale Tempco
1
ANALOG INPUT
Input Voltage Range
Input Current Range
POWER SUPPLIES
Positive Supply Current
Negative Supply Current
Power Consumption
Power Supply Rejection Ratio
DIGITAL INPUTS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
Digital Input Capacitance
DIGITAL OUTPUTS
Logic Input High Voltage
Logic Input Low Voltage
Three-State Output Leakage
Digital Input Capacitance
DYNAMIC PERFORMANCE
Conversion Time
Symbol
INL
DNL
V
ZSE
G
FSE
TCG
FS
V
IN
I
IN
I
DD
I
SS
P
DISS
PSRR+
PSRR–
V
INH
V
INL
I
IN
C
IN
V
OH
V
OL
I
OZ
C
OUT
TC
Conditions
Min
–1
–1
–5
–6
Typ
V
DD
= +5 V, V
SS
= –12 V
V
DD
= +5 V, V
SS
= –12 V
5
0
0
V
DD
= +5 V
2
V
SS
= –12 V
2
V
DD
= +5 V
2
, V
SS
= –12 V
2
∆V
DD
=
±
5%, A
IN
= 10 V
∆V
SS
=
±
5%, A
IN
= 10 V
CS, RD,
HBEN
CS, RD,
HBEN
CS, RD,
HBEN
Digital Inputs,
CS, RD,
HBEN, CLKIN
I
SOURCE
= 0.2 mA
I
SINK
= 1.6 mA
D
11
–D
0/8
D
11
–D
0/81
f
CLK
= 1.25 MHz
3
Synchronous Clock
Asynchronous Clock
2.4
5
3
70
1/2
1/2
7
5
95
4
4
7
4
0.8
±
1
10
8
0.4
10
15
10.4
10.4
11.2
µs
µs
NOTES
1
Guaranteed by design.
2
Converter inactive;
CS, RD
= High, A
IN
= 10 V.
3
See Synchronizing Start Conversion information in Converter Operation Details. Typicals (typ) are median values measured at 25
°C.
See Typical Performance
Characteristics for additional information.
Specifications subject to change without notice.
5V
3k
DBN
3k
DGND
A. HIGH-Z TO V
OH
(
t
3
)
AND V
OL
TO V
OH
(
t
6
)
C
L
DBN
C
L
DGND
B. HIGH-Z TO V
OL
(
t
3
)
AND V
OH
TO V
OL
(
t
6
)
5V
3k
DBN
3k
DGND
A. V
OH
TO HIGH-Z
10pF
DBN
10pF
DGND
B. V
OL
TO HIGH-Z
Figure 3. Load Circuits for Access Time
Figure 4. Load Circuits for Output Float Delay
–2–
REV. B
ADC912A
(V
DD
= +5 V 5%, V
SS
= –11.4 V to –15.75 V, V
REFIN
= –5 V, Analog Input 0 V to 10 V;
External f
CLK
= 1.25 MHz; –40 C to +85 C applies to ADC912A/F unless otherwise noted. See Figures 5 to 8.)
Parameter
CS
to
RD
Setup Time
RD
to
BUSY
Propagation Delay
Data Access Time after READ
Read Pulsewidth
CS
to
RD
Hold Time
New Data Valid after
BUSY
Bus Disconnect Time
HBEN to
RD
Setup Time
HBEN to
RD
Hold Time
Delay between Successive Read Operations
Symbol
t
1
t
2
t
3 3
t
4 3
t
5
t
6 3
t
7
t
8
t
9
t
10
Conditions
Min
0
C
L
= 100 pF
90
0
C
L
= 100 pF
20
20
20
350
–30
60
0
90
65
150
125
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING CHARACTERISTICS
1, 2
250
NOTES
1
Guaranteed by design.
2
All input control signals are specified with t
R
= t
F
= 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
3
t
3
, t
4
, and t
6
are measured with the load circuits of Figure 3 and timed for and output to cross 0.8 V or 2.4 V.
4
t
7
is the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 4.
Specifications subject to change without notice.
CS
TIMING DIAGRAMS
CS
RD
t
1
t
5
t
4
t
2
t
1
t
4
t
5
t
1
RD
t
5
t
10
t
CONV
t
6
OLD DATA
DB
11
– DB
0
D
10
D
9
D
8
D
7
t
1
BUSY
t
CONV
t
7
OLD DATA
DB
11
– DB
0
t
2
t
3
t
CONV
t
2
BUSY
t
3
DATA
t
7
NEW DATA
DB
11
– DB
0
t
3
DATA
DATA D
OUTPUTS
11
t
7
NEW DATA
DB
11
– DB
0
D
6
D
5
D
4
D
3/11
D
2/10
D
1/9
D
0/8
DATA D
OUTPUTS
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3/11
D
2/10
D
1/9
D
0/8
FIRST READ
DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
(OLD DATA)
SECOND DB DB DB DB DB DB DB DB DB DB DB DB
11
10
9
8
7
6
5
4
3
2
1
0
READ
READ DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
Figure 5. Parallel Read Timing Diagram, Slow-Memory
Mode (HBEN = LOW)
Figure 7. Parallel Read Timing Diagram, ROM Mode
(HBEN = LOW)
HBEN
t
8
HBEN
CS
t
9
t
8
t
9
t
8
t
9
t
8
CS
t
9
t
5
t
10
t
7
t
6
OLD DATA
DB
7
– DB
0
NEW DATA
DB
7
– DB
0
t
8
t
9
RD
t
1
t
4
t
2
BUSY
t
5
t
1
t
4
t
5
t
1
t
4
t
10
t
2
t
5
t
1
RD
t
1
t
4
t
5
t
CONV
t
3
t
7
OLD DATA
DB
7
– DB
0
t
2
BUSY
t
CONV
t
3
t
7
NEW DATA
DB
11
– DB
8
t
3
t
7
NEW DATA
DB
7
– DB
0
t
3
DATA
t
3
t
7
DATA
NEW DATA
DB
11
– DB
8
D
3/11
DB
3
DB
11
D
2/10
DB
2
DB
10
D
1/9
DB
1
DB
9
D
0/8
DB
0
DB
8
DATA
OUTPUTS
FIRST READ
SECOND READ
D
7
DB
7
LOW
D
6
DB
6
LOW
D
5
DB
5
LOW
D
4
DB
4
LOW
DATA
OUTPUTS
FIRST READ
(OLD DATA)
SECOND READ
THIRD READ
D
7
DB
7
LOW
DB
7
D
6
DB
6
LOW
DB
6
D
5
DB
5
LOW
DB
5
D
4
DB
4
LOW
DB
4
D
3/11
DB
3
DB
11
DB
3
D
2/10
DB
2
DB
10
DB
2
D
1/9
DB
1
DB
9
DB
1
D
0/8
DB
0
DB
8
DB
0
Figure 6. Two-Byte Read Timing Diagram, Slow-Memory
Mode
Figure 8. Two-Byte Read Timing Diagram, ROM Mode
REV. B
–3–
ADC912A
ABSOLUTE MAXIMUM RATINGS
(T
A
= 25°C, unless otherwise noted)
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
SS
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
V
REFIN
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
to V
DD
AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
A
IN
to AGND . . . . . . . . . . . . . . . . . . . . . . . . –15 V to +15 V
Digital Input Voltage to DGND,
Pins 17, 19–21 . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Output Voltage to DGND,
Pins 4–11, 13–16, 18, 22 . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Extended Industrial: ADC912A/F . . . . . . . –40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Maximum Junction Temperature (T
J
max) . . . . . . . . . . 150°C
Package Power Dissipation . . . . . . . . . . . . . . (T
J
max–T
A
)/θ
JA
Thermal Resistance
θ
JA
Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W
SOIC-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C
ORDERING GUIDE
Model
ADC912AFP
ADC912AFS
Temperature
Range
–40°C to +85°C
–40°C to +85°C
INL
(LSB)
±
1
±
1
Package Description
24-Lead Narrow-Body Plastic
24-Lead Wide-Body SOIC
Package
Option
N-24
R-24
Table I. Analog Input to Digital Output Code Conversion
Analog Input Voltage
0 V to 10 V
–10 V to +10 V
+FS – 1 LSB
+FS – 1 1/2 LSB
Midscale + 1/2 LSB
Midscale
–FS + 1/2 LSB
–FS
9.9976
9.9964
5.0012
5.0000
0.0012
0.0000
9.99951
9.9927
0.0024
0.0000
–9.9976
–10.000
Output Code*
DB
11
(MSB) DB
0
(LSB)
1111 1111 1111
1 1 1 1 1 1 1 1 1111φ
1000 0000 000
φ
1000 0000 0000
0000 0000 000
φ
0000 0000 0000
*The
symbol”φ” indicates a 0 or 1 with equal probability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADC912A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. B
ADC912A
WAFER TEST LIMITS
(@ V
Parameter
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Analog Input Resistance
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
Logic Output High Voltage
Logic Output Low Voltage
Positive Supply Current
Negative Supply Current
DD
= +5 V, V
SS
= –12 V or –15 V, V
REF
= –5 V, A
IN
= 0 V to 10 V, and T
A
= 25 C, unless otherwise noted.)
Conditions
ADC912AG
Limit
±
1
±
1
±
8
±
8
4/6
2.4
0.8
±
1
4
0.4
7
5
Unit
LSB max
LSB max
LSB max
LSB max
kΩ min/max
V min
V max
µA
max
V min
V max
mA max
mA max
Symbol
INL
DNL
V
ZSE
G
FSE
R
AIN
V
INH
V
INL
I
IN
V
OH
V
OL
I
DD
I
SS
Guaranteed by Design
CS, RD,
HBEN
CS, RD,
HBEN
CS, RD,
HBEN
I
SOURCE
= 0.2 mA
I
SINK
= 1.6 mA
V
DD
= +5 V,
CS
=
RD
= V
DD
, A
IN
= +10 V
V
SS
= –12 V,
CS
=
RD
= V
DD
, A
IN
= +10 V
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
10V
C1
–5V
C1
R
+
C2
R
+
C2
1
2
3
4
5
6
24
23
R
C1
R
+
C2
+
C2
+5V
–15V
C1
22
NC
21
R
R
ADC912A
20
NC
7
8
9
10
11
TOP VIEW
19
(Not to Scale)
17
18
NC
R
16
NC
15
NC
14
NC
13
NC
R = 10
C1 = 0.01 F
C2 = 4.7 F
NC = NO CONNECT
POWER SUPPLY SEQUENCE:
+5V, –15V, –5V, +10V
12
Figure 9. Burn-In Circuit
REV. B
–5–
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