ADC1210S080HN/C1 datasheet, PDF

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ADC1210S080HN/C1: DescriptionSingle 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs; CategoryAnalog mixed-signal IC converter; File Size235KB，36 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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ADC1210S080HN/C1 Overview

Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs

ADC1210S080HN/C1 Parametric

Parameter Name	Attribute value
Maker	NXP
Parts packaging code	QFN
package instruction	HVQCCN,
Contacts	40
Reach Compliance Code	unknow
ECCN code	EAR99
Maximum analog input voltage	2 V
Minimum analog input voltage
Converter type	ADC, PROPRIETARY METHOD
JESD-30 code	S-PQCC-N40
length	6 mm
Number of analog input channels	1
Number of digits	12
Number of functions	1
Number of terminals	40
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output bit code	OFFSET BINARY, 2\'S COMPLEMENT BINARY, GRAY CODE
Output format	SERIAL, PARALLEL, WORD
Package body material	PLASTIC/EPOXY
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Certification status	Not Qualified
Sampling rate	80 MHz
Sample and hold/Track and hold	SAMPLE
Maximum seat height	1 mm
Nominal supply voltage	3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
width	6 mm

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ADC1210S series

Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;

CMOS or LVDS DDR digital outputs

Rev. 01 — 9 April 2010

Preliminary data sheet

1. General description

The ADC1210S is a single-channel 12-bit Analog-to-Digital Converter (ADC) optimized for

high dynamic performances and low power consumption at sample rates up to 125 Msps.

Pipelined architecture and output error correction ensure the ADC1210S is accurate

enough to guarantee zero missing codes over the entire operating range. Supplied from a

single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode,

thanks to a separate digital output supply. It supports the Low Voltage Differential

Signalling (LVDS) Double Data Rate (DDR) output standard. An integrated

Serial Peripheral Interface (SPI) allows the user to easily configure the ADC. The device

also includes a SPI programmable full-scale to allow flexible input voltage range from 1 V

to 2 V (peak-to-peak). With excellent dynamic performance from the baseband to input

frequencies of 170 MHz or more, the ADC1210S is ideal for use in communications,

imaging and medical applications.

2. Features and benefits

SNR, 70 dBFS; SFDR, 86 dBc

Sample rate up to 125 Msps

12-bit pipelined ADC core

Clock input divider by 2 for less jitter

contribution

Single 3 V supply

Flexible input voltage range: 1 V p-p to

2 V p-p

CMOS or LVDS DDR digital outputs

Pin compatible with the ADC1410S

series and the ADC1010 series

HVQFN40 package

Input bandwidth, 600 MHz

Power dissipation, 430 mW at 80 Msps

Serial Peripheral Interface (SPI)

Duty cycle stabilizer

Fast OuT of Range (OTR) detection

INL

±0.25

LSB, DNL

±0.12

LSB

Offset binary, two’s complement, gray

code

Power-down and Sleep modes

3. Applications

Wireless and wired broadband

communications

Spectral analysis

Ultrasound equipment

Portable instrumentation

Imaging systems

Software define radio

ADC1210S080HN/C1 Related Products

	ADC1210S080HN/C1	ADC1210S	ADC1210S105HN/C1	ADC1210S065HN/C1	ADC1210S125HN/C1
Description	Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs	Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs	Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs	Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs	Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs
Maker	NXP	-	NXP	NXP	NXP
Parts packaging code	QFN	-	QFN	QFN	QFN
package instruction	HVQCCN,	-	HVQCCN,	HVQCCN,	HVQCCN,
Contacts	40	-	40	40	40
Reach Compliance Code	unknow	-	unknow	unknow	unknow
ECCN code	EAR99	-	EAR99	EAR99	EAR99
Maximum analog input voltage	2 V	-	2 V	2 V	2 V
Converter type	ADC, PROPRIETARY METHOD	-	ADC, PROPRIETARY METHOD	ADC, PROPRIETARY METHOD	ADC, PROPRIETARY METHOD
JESD-30 code	S-PQCC-N40	-	S-PQCC-N40	S-PQCC-N40	S-PQCC-N40
length	6 mm	-	6 mm	6 mm	6 mm
Number of analog input channels	1	-	1	1	1
Number of digits	12	-	12	12	12
Number of functions	1	-	1	1	1
Number of terminals	40	-	40	40	40
Maximum operating temperature	85 °C	-	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-	-40 °C	-40 °C	-40 °C
Output bit code	OFFSET BINARY, 2\'S COMPLEMENT BINARY, GRAY CODE	-	OFFSET BINARY, 2\'S COMPLEMENT BINARY, GRAY CODE	OFFSET BINARY, 2\'S COMPLEMENT BINARY, GRAY CODE	OFFSET BINARY, 2\'S COMPLEMENT BINARY, GRAY CODE
Output format	SERIAL, PARALLEL, WORD	-	SERIAL, PARALLEL, WORD	SERIAL, PARALLEL, WORD	SERIAL, PARALLEL, WORD
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	HVQCCN	-	HVQCCN	HVQCCN	HVQCCN
Package shape	SQUARE	-	SQUARE	SQUARE	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	-	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Certification status	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified
Sampling rate	80 MHz	-	105 MHz	65 MHz	125 MHz
Sample and hold/Track and hold	SAMPLE	-	SAMPLE	SAMPLE	SAMPLE
Maximum seat height	1 mm	-	1 mm	1 mm	1 mm
Nominal supply voltage	3 V	-	3 V	3 V	3 V
surface mount	YES	-	YES	YES	YES
Temperature level	INDUSTRIAL	-	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	NO LEAD	-	NO LEAD	NO LEAD	NO LEAD
Terminal pitch	0.5 mm	-	0.5 mm	0.5 mm	0.5 mm
Terminal location	QUAD	-	QUAD	QUAD	QUAD
width	6 mm	-	6 mm	6 mm	6 mm

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