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CY74FCT273ATSOCE4

Description
D Flip-Flop, FCT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20, GREEN, SOIC-20
Categorylogic    logic   
File Size470KB,13 Pages
ManufacturerRochester Electronics
Websitehttps://www.rocelec.com/
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CY74FCT273ATSOCE4 Overview

D Flip-Flop, FCT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20, GREEN, SOIC-20

CY74FCT273ATSOCE4 Parametric

Parameter NameAttribute value
MakerRochester Electronics
package instructionSOP,
Reach Compliance Codeunknown
seriesFCT
JESD-30 codeR-PDSO-G20
length12.8 mm
Logic integrated circuit typeD FLIP-FLOP
Number of digits8
Number of functions1
Number of terminals20
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
propagation delay (tpd)7.2 ns
Maximum seat height2.65 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Trigger typePOSITIVE EDGE
width7.5 mm
CY54FCT273T, CY74FCT273T
8-BIT REGISTERS
SCCS020A – MARCH 1995 – REVISED OCTOBER 2001
D
D
D
D
D
D
D
D
D
Function, Pinout, and Drive Compatible
With FCT and F Logic
Reduced V
OH
(Typically = 3.3 V) Versions
of Equivalent FCT Functions
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
I
off
Supports Partial-Power-Down Mode
Operation
Matched Rise and Fall Times
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Fully Compatible With TTL Input and
Output Logic Levels
CY54FCT273T
– 32-mA Output Sink Current
– 12-mA Output Source Current
CY74FCT273T
– 64-mA Output Sink Current
– 32-mA Output Source Current
CY54FCT273T . . . D PACKAGE
CY74FCT273T . . . Q OR SO PACKAGE
(TOP VIEW)
MR
Q
0
D
0
D
1
Q
1
Q
2
D
2
D
3
Q
3
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
Q
7
D
7
D
6
Q
6
Q
5
D
5
D
4
Q
4
CP
CY54FCT273T . . . L PACKAGE
(TOP VIEW)
MR
V
CC
D
0
Q
0
description
The ’FCT273T devices consist of eight
edge-triggered D-type flip-flops with individual
D inputs and Q outputs. The common
buffered-clock (CP) and master-reset (MR) inputs
load and reset all flip-flops simultaneously. These
devices are edge-triggered registers. The state of
each D input (one setup time before the
low-to-high clock transition) is transferred to the
corresponding flip-flop’s Q output. All outputs are
forced low by a low logic level on the MR input.
This
device
is
fully
specified
for
partial-power-down applications using I
off
. The I
off
circuitry disables the outputs, preventing
damaging current backflow through the device
when it is powered down.
D
1
Q
1
Q
2
D
2
D
3
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
Q
7
D
7
D
6
Q
6
Q
5
D
5
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Q
3
GND
CP
Q
4
D
4
1

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