Preliminary and proprietary Information of YAMAR Electronics Ltd. Subject to change without notice.
YAMAR
Ele c tro ni cs L td
Preliminary
Data Sheet
SIG61 - Smart Slave for
DC-BUS Powerline Network
This information is preliminary and may be changed without notice
1 GENERAL
The SIG61 is an independent slave in a DC-BUS Powerline communication network controlled by a
SIG60 master device. The SIG61 has 4 identification (ID) pins, used to set the device address, 8 input
pins and 8 output pins. The master can access any SIG61 device independently by using the proper
device address. Data received from a remote SIG60 Master device is reflected to its output pins. The
Master device can read the SIG61 input pins remotely. Its small footprint integrates most of the
components needed for proper operation allowing small-size control solutions.
The SIG61 is an economical slave device for applications such as controlling motors, reading sensors
etc., eliminating the need for dedicated control wires and a host controller for its operation. It helps
reducing the harness size and increase reliability. The SIG61 has a sleep mode that enables power
saving; special Wakeup messages on the DC line are used to signal the sleeping devices to return to
normal operation mode.
The SIG61 is useful for a wide range of Automotive, Avionics and Industrial applications such as sensor
reading, actuator activation, doors, seats, mirrors, climate control, lights, Truck-Trailer, etc.
Host
Master
8
ID
4
8
8
ID
4
8
SIG61
SIG61
Battery Power Line
Figure 1.1 - SIG61 Application example
Applications
•
•
•
•
•
•
•
•
Truck-Trailer sub-bus
Door module
Climate control network
Front and back Lights
Sensors Actuators network
Entertainment control
Green Energy management
Security Monitoring
Features
•
•
•
•
•
•
•
•
•
7 selectable Carrier frequencies 1.75MHz - 13MHz
Selectable bit rate between 9.6 Kbps to 115.2 Kbps.
8 output and 8 input pins
Eliminates data wires and transceiver.
Operates over wide range of noisy power supply / battery lines.
Byte oriented communication.
Sleep Mode for low power consumption.
Allows Master - Slave multiplex networks
Several independent networks can operate over the same wire
using different carrier frequencies.
•
Small footprint QFN 64 pin package
© 2010 Yamar Electronics Ltd.
1
DS-SIG61 R0.932
Preliminary and proprietary Information of YAMAR Electronics Ltd. Subject to change without notice.
2 OVERVIEW
The SIG61 is an independent slave in a Master-Slaves network operating on a selected narrow band
channel. A single SIG60 master controls all the slaves in a network; the slaves may be SIG61 devices
as well as SIG60 devices operating as slaves.
Proper Network operation is maintained by employing 5 types of command messages:
Read, Read-
change, Write, Sleep
and
Change-Frequency.
The command format is similar to the standard Universal
Asynchronous Receiver Transmitter (UART).
The SIG61 has internal narrow band modem, capable of operating in noisy environments. The receiver
listens to the DC-BUS on its preset frequency. It filters out the signal from noise and interference and
tries to recover the original command. If the checksum is correct, the SIG61 extracts the ID, Command
and the Data.
If the received ID matches its own ID, the SIG61 proceeds to detect the received command. When a
Write command is received, the data part of the command is directed to the corresponding 8 output
pins. When a Read command is detected, the SIG61 responds by transmitting a dedicated message
towards the master containing an image of its 8 input pins.
Multiple networks can operate concurrently on the same wire using different carrier frequencies.
2.1
Channels and Network
The SIG60-SIG61 network supports 16 combinations of frequency pairs. When set to such a pair, it is
easy to switch from one frequency to the other when such need arises. Each channel accommodates a
single SIG60 master and up to 15 SIG61/SIG60 slave devices. Additional SIG60-SIG61 networks can
coexist on the same power line by employing different frequencies for each network, thus allowing
different applications.
Channel frequencies: 1.75MHz, 4.5MHz, 5.5MHz, 6.0MHz, 6.5MHz, 10.5MHz and 13.0MHz.
Data transfer rate:
9.6Kbps up to 115.2Kbps.
Cable length: Dependant on external AC loads connected to the DC line.
2.2
The SIG61 Device
Figure 2.1 outlines the building blocks of the SIG61 device.
Figure 2.1 - SIG61 Logical Blocks
© 2010 Yamar Electronics Ltd.
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DS-SIG61 R0.932
Preliminary and proprietary Information of YAMAR Electronics Ltd. Subject to change without notice.
3 SIG61 SIGNALS
Device signals are described in table 3.1.
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
INH
nSleep
AutoSleep
nReset
Out0
Out1
Wake
Out2
Out3
MF1nF0
Out4
Out5
TxOn
Out6
Out7
RxOn
F0F1-0
F0F1-1
Gnd
OscO
OscIn
AGnd
F0F1-2
F0F1-3
Vcc
F1B
F0B
AVdd
RxP
Mode3
Mode4
AutoFreqCh
Gnd
Vdd
HDO
In7
In6
F1nF0
In5
In4
In3_HDC
In2_HDI
Vdd
In1
DTxO
Gnd
In0
Mode2_LBD
SIG61
Id0
Test
Id1
Id2
Id3
Vdd
RxIn
RxN
TxO
Gnd
Gnd
NC
Vdd
InterHope
BitRate1
BitRate0
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
EXP
EXP
Pin name
HDO
INH
Pin# Pin type
35
32
Output
8mA
Output
8mA
Input
Input
nSleep
Wake
31
26
Control Signals
Digital data output signal. Output the received data from the
powerline to the host.
Inhibit output for enabling the host or an external voltage regulator
powering the host. This signal is HIGH in the normal and standby
modes and LOW in sleep mode.
Sleep control input. Pulling this signal to LOW puts the SIG61 in
sleep mode. Should be pulled to Vdd.
Local wakeup input. Negative or positive edge triggered. This pin can
be connected to an external switch in the application. When the pin is
triggered the device will wake up and send a wake up message to all
the devices on the network. When not in use, this pin should be
pulled Up or Down.
is detected on the DC line. When HIGH, detection of interference
switches the operating frequency between F0 and F1. If at the new
frequency, no reception occurred for 2 sec, the operating frequency is
switched back. For designs with a single channel this pin should be
tied to ground.
nReset
InterfHop
29
3
Input, PU Reset Input
Input, PD
Allows automatic frequency hoping whenever an interference signal
Test
MF1nF0
15
23
OscO
52
Input, PD Should be connected to Gnd
Output
Output indicating the operating frequency. F1 when HIGH and F0
12mA
when LOW.
Line Interface signals
Analog Crystal Output
Output
© 2010 Yamar Electronics Ltd.
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Figure 3.1 - SIG61 Pin-out
Description
3
DS-SIG61 R0.932
Preliminary and proprietary Information of YAMAR Electronics Ltd. Subject to change without notice.
OscIn
RxN
RxP
DTxO
RxIn
TxO
F0B
F1B
TxOn
RxOn
In0
In1
In2_HDI
In3_HDC
In4
In5
In6
In7
Out0
Out1
Out2
Out3
Out4
Out5
Out6
Out7
53
9
61
45
10
8
59
58
20
17
47
44
42
41
40
39
37
36
28
27
25
24
22
21
19
18
Analog
Input
Analog
Output
Analog
Input
Tristate/
Output
2mA
Analog
Input
Analog
Output
Analog, Bi
directional
Analog, Bi
directional
Output
12mA
Output
12mA
Crystal Input
The internal comparator negative pin. Its value is internally pulled to
Vdd/2. Bypass RxN to Ground with a 1nF capacitor.
Positive pin input signal. Should be tied to RxN with a 1K Ohm
resistor.
Modulated digital transmit signal output to both ceramic filters.
Receive input
from the DC-BUS to the RX operational amplifier. This
input is pulled internally to Vdd/2.
Transmit output.
F0 External filter I/O. Its value is internally pulled to Vdd/2.
F1 External filter I/O. Its value is internally pulled to Vdd/2.
HIGH when the device is transmitting a message.
HIGH when the device is in receive mode.
I/O Signals
Input PD
The pin is read by the Master with a Read or Read-Change
Input PD
Input
Input
Input PD
Input PD
Input PD
Input PD
Output
8mA
Output
8mA
Output
8mA
Output
8mA
Output
8mA
Output
8mA
Output
8mA
Output
8mA
Input PD
Input PD
Input PD
Input PD
command.
The pin is read by the Master with a Read or Read-Change
command.
The pin is read by the Master with a Read or Read-Change
command.
When in SIG60 mode, HDI input.
The pin is read by the Master with a Read or Read-Change
command.
When in SIG60 mode, HDC input.
The pin is read by the Master with a Read or Read-Change
command.
The pin is read by the Master with a Read or Read-Change
command.
The pin is read by the Master with a Read or Read-Change
command.
The pin is read by the Master with a Read or Read-Change
command.
Output of data bit 0 when the Write command received from Master.
Output of data bit 1 when the Write command received from Master.
Output of data bit 2 when the Write command received from Master.
Output of data bit 3 when the Write command received from Master.
Output of data bit 4 when the Write command received from Master.
Output of data bit 5 when the Write command received from Master.
Output of data bit 6 when the Write command received from Master.
Output of data bit 7 when the Write command received from Master.
Configuration Signals
Id0
Id1
Id2
Id3
16
14
13
12
SIG61 bit 0 ID address in the network.
SIG61 bit 1 ID address in the network.
SIG61 bit 2 ID address in the network.
SIG61 bit 3 ID address in the network.
© 2010 Yamar Electronics Ltd.
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DS-SIG61 R0.932
Preliminary and proprietary Information of YAMAR Electronics Ltd. Subject to change without notice.
F0F1-0
F0F1-1
F0F1-2
F0F1-3
BitRate0
BitRate1
NC
Mode2
Mode3
Mode4
AutoFreqCh
AutoSleep
F1nF0
Gnd
Vdd
AGnd
AVdd
Exp
49
50
55
56
1
2
5
48
62
36
64
Should be left unconnected.
Should be connected to Vdd.
Should be connected to Vdd
Automatic Frequency Change. When HIGH, the device automatically
switches frequency after about 4 seconds without bus activity.
30 Input PD
When this pin is set to HIGH, the device will automatically enter sleep
mode after about 8 seconds without bus activity.
Input PD
Input PD
Input PD
Input PD
Input PD
Input PD
---
Input PD
Input PD
Input PD
Input PD
Frequency selection pins. See 4.2.
Frequency selection pins. See 4.2.
Frequency selection pins. See 4.2.
Frequency selection pins. See 4.2.
Bit rate selection pins. See 4.3.
Bit rate selection pins. See 4.3.
Not connected.
Input PD Selects between F0 / F1. HIGH – F1, LOW – F0
Power signals
4,11, Power
Ground
34,43,
57
6,7,33, Power
3.3V power supply.
46,51
54
Power
Analog Ground
60
Power
3.3V Analog Power. Separate from Vdd with a 10 Ohm resistor and bypass
to Ground with 1nF and 10nF capacitor.
Exp
May be connected to GND
38
PD – Pull down resistor 100K ohm ±%30
PU – Pull up resistor 100K ohm ±%30
Table 3.1 - Device signals
3.1 Power Signals
Vdd and Gnd layout traces should be as wide as possible. It is recommended to connect a 0.1uF
capacitor between each Vdd and ground pins, as close as possible to the pins.
Analog Vdd pin, AVdd, should be connected to Vdd. AGnd should be connected to ground. The Analog
supply has to be sufficiently powerful (capable of current driving), to avoid any fluctuations of supply
voltage level. It is recommended to keep the lines connecting the 3.3V power supply to Vdd pins as
short as possible with wide PCB traces.
AVdd
Vdd
R3
10
C5
1n
C6
10n
Figure 3.2 - Recommended AVdd circuitry
© 2010 Yamar Electronics Ltd.
5
DS-SIG61 R0.932
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