IRFF220
Data Sheet
March 1999
File Number
1889.3
3.5A, 200V, 0.800 Ohm, N-Channel
Power MOSFET
Title
FF2
b-
t
5A,
0V,
00
m,
an-
wer
OS-
T)
utho
ey-
rds
5A,
0V,
00
m,
an-
wer
OS-
T,
er-
rpo-
on,
-
5AF
e-
r ()
OCI
This N-Channel enhancement mode silicon gate power field
effect transistor is an advanced power MOSFET designed,
tested, and guaranteed to withstand a specified level of
energy in the breakdown avalanche mode of operation. All of
these power MOSFETs are designed for applications such
as switching regulators, switching convertors, motor drivers,
relay drivers, and drivers for high power bipolar switching
transistors requiring high speed and low gate drive power.
These types can be operated directly from integrated
circuits.
Formerly developmental type TA9600.
Features
• 3.5A, 200V
• r
DS(ON)
= 0.800
Ω
• Single Pulse Avalanche Energy Rated
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Ordering Information
PART NUMBER
IRFF220
PACKAGE
TO-205AF
BRAND
IRFF220
Symbol
D
NOTE: When ordering, include the entire part number.
G
S
Packaging
JEDEC TO-205AF
DRAIN
(CASE)
GATE
SOURCE
©2001 Fairchild Semiconductor Corporation
IRFF220 Rev. A
IRFF220
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
IRFF220
200
200
3.5
14
±
20
20
0.16
85
-55 to 150
300
260
UNITS
V
V
A
A
V
W
W/
o
C
mJ
o
C
o
C
o
C
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
DS
Drain to Gate Voltage (R
GS
= 20k
Ω)
(Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
D
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E
AS
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 125
o
C.
Electrical Specifications
PARAMETER
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
BV
DSS
V
GS(TH)
I
DSS
I
D(ON)
I
GSS
r
DS(ON)
g
fs
t
d(ON)
t
r
t
d(OFF)
t
f
Q
g(TOT)
Q
gs
Q
gd
C
ISS
C
OSS
C
RSS
L
D
Measured from the
Drain Lead, 5mm (0.2in)
from Header to Center
of Die
Measured from the
Source Lead, 5mm
(0.2in) from Header and
Source Bonding Pad
Modified MOSFET
Symbol Showing the
Internal Device
Inductances
D
L
D
G
L
S
S
TEST CONDITIONS
V
GS
= 0V, I
D
= 250
µ
A (Figure 10)
V
GS
= V
DS
, I
D
= 250
µ
A
V
DS
= Rated BV
DSS
, V
GS
= 0V
V
DS
= 0.8 x Rated BV
DSS
, V
GS
= 0V, T
J
= 125
o
C
V
DS
> I
D(ON) x
r
DS(ON)MAX
, V
GS
= 10V (Figure 7)
V
GS
=
±
20V
V
GS
= 10V, I
D
= 2.0A (Figures 8, 9)
V
DS
> I
D(ON) x
r
DS(ON)MAX
, I
D
= 2.0A (Figure 12)
V
DD
= 0.5 x Rated BV
DSS
, R
G
= 9.1
Ω
,
V
GS
= 10V, I
D
≈
3.5A (Figures 17, 18)
R
L
= 27.4
Ω
for V
DSS
= 100V,
R
L
= 20.3
Ω
for V
DSS
= 75V,
MOSFET Switching Times are Essentially
Independent of Operating Temperature
V
GS
= 10V, I
D
= 3.5A, V
DS
= 0.8 x Rated BV
DSS,
I
g(REF)
= 1.5mA (Figures 14, 19, 20) Gate Charge
is Essentially Independent of Operating
Temperature
V
GS
= 0V, V
DS
= 25V, f = 1.0MHz (Figure 11)
MIN
200
2.0
-
-
3.5
-
-
1.5
-
-
-
-
-
-
-
-
-
-
-
TYP
-
-
-
-
-
-
0.5
2.25
20
30
50
30
11
5.0
6.0
450
150
40
5.0
MAX
-
4.0
25
250
-
±
±
100
0.800
-
40
60
100
60
15
-
-
-
-
-
-
UNITS
V
V
µ
A
µ
A
A
nA
Ω
S
ns
ns
ns
ns
nC
nC
nC
pF
pF
pF
nH
Drain to Source Breakdown Voltage
Gate to Threshold Voltage
Zero-Gate Voltage Drain Current
On-State Drain Current (Note 2)
Gate to Source Leakage Forward
Drain to Source On Resistance (Note 2)
Forward Transconductance (Note 2)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
(Gate to Source + Gate to Drain)
Gate to Source Charge
Gate to Drain “Miller” Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Internal Drain Inductance
Internal Source Inductance
L
S
-
15
-
nH
Junction to Case
Junction to Ambient
R
θ
JC
R
θ
JA
Free Air Operation
-
-
-
-
6.25
175
o
C/W
o
C/W
©2001 Fairchild Semiconductor Corporation
IRFF220 Rev. A
IRFF220
Source to Drain Diode Specifications
PARAMETER
Continuous Source to Drain Current
Pulse Source to Drain Current (Note 3)
SYMBOL
I
SD
I
SDM
TEST CONDITIONS
Modified MOSFET
Symbol Showing the
Integral Reverse P-N
Junction Rectifier
D
MIN
-
-
TYP
-
-
MAX
3.5
14
UNITS
A
A
G
S
Source to Drain Diode Voltage (Note 2)
Reverse Recovery Time
Reverse Recovered Charge
NOTES:
V
SD
t
rr
Q
RR
T
J
= 25
o
C, I
SD
= 3.5A, V
GS
= 0V (Figure 13)
T
J
= 150
o
C, I
SD
= 3.5A, dI
SD
/d
t
= 100A/
µ
s
T
J
= 150
o
C, I
SD
= 3.5A, dI
SD
/d
t
= 100A/µs
-
-
-
-
350
2.3
2.0
-
-
V
ns
µC
2. Pulse test: pulse width
≤
300µs, duty cycle
≤
2%.
3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. V
DD
= 20V, start T
J
= 25
o
C, L = 12.5mH, R
G
= 50ΩΩ, peak I
AS
= 3.5A (Figures 15, 16).
Typical Performance Curves
1.2
POWER DISSIPATION MULTIPLIER
1.0
I
D
, DRAIN CURRENT (A)
0
50
100
150
5
4
0.8
0.6
0.4
0.2
0
3
2
1
0
25
50
75
100
125
150
T
C
, CASE TEMPERATURE (
o
C)
T
C
, CASE TEMPERATURE (
o
C)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
Z
θJC,
NORMALIZED TRANSIENT
1.0
THERMAL IMPEDANCE
0.5
0.2
0.1
0.1
0.05
0.02
0.01
SINGLE PULSE
0.01
10
-5
10
-4
10
-3
10
-2
0.1
P
DM
t
1
t
2
NOTES:
DUTY FACTOR: D = t
1
/t
2
T
J
= P
DM
x Z
θJC
x R
θJC
+ T
C
1
10
t
1
, SQUARE WAVE PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2001 Fairchild Semiconductor Corporation
IRFF220 Rev. A
IRFF220
Typical Performance Curves
50
(Continued)
10
10V
80µs PULSE TEST
10µs
100µs
8
V
GS
= 6V
V
GS
= 7V
I
D
, DRAIN CURRENT (A)
10
I
D
, DRAIN CURRENT (A)
6
1.0
OPERATION IN THIS
AREA IS LIMITED
BY r
DS(ON)
1ms
4
V
GS
= 5V
10ms
100ms
T
C
= 25
o
C
DC
0.1 T
J
= MAX RATED
SINGLE PULSE
0.05
1
10
100
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
2
V
GS
= 4V
0
0
20
40
60
80
100
1000
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. OUTPUT CHARACTERISTICS
5
80µs PULSE TEST
4
V
GS
= 10V
8V
I
D
, ON-STATE DRAIN CURRENT (A)
V
GS
= 6V
10
V
DS
> I
D(ON)
x r
DS(ON)
MAX
80µs PULSE TEST
8
I
D
, DRAIN CURRENT (A)
3
V
GS
= 5V
6
2
4
T
J
= 125
o
C
2
T
J
= -25
o
C
T
J
= -55
o
C
1
V
GS
= 4V
0
0
2
4
6
8
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
10
0
0
2
4
6
8
V
GS
, GATE TO SOURCE VOLTAGE (V)
10
FIGURE 6. SATURATION CHARACTERISTICS
FIGURE 7. TRANSFER CHARACTERISTICS
1.5
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
CURRENT PULSE 2µs
T
J
= 25
o
C
r
DS(ON),
DRAIN TO SOURCE
ON RESISTANCE (Ω)
2.2
I
D
= 2A
V
GS
= 10V
1.8
1.0
V
GS
= 10V
1.4
0.5
V
GS
= 20V
1.0
0.6
0.2
0
5
15
10
I
D
, DRAIN CURRENT (A)
20
-40
0
40
80
120
160
T
J
, JUNCTION TEMPERATURE (
o
C)
NOTE: Heating effect of 2µs pulse is minimal.
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
©2001 Fairchild Semiconductor Corporation
IRFF220 Rev. A
IRFF220
Typical Performance Curves
1.25
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
I
D
= 250µA
(Continued)
1000
V
GS
= 0V, f = 1MHz
C
ISS
= C
GS
+ C
GD
C
RSS
= C
GD
C
OSS
≈
C
DS
+ C
GS
1.05
C, CAPACITANCE (pF)
1.15
800
600
C
ISS
400
0.95
0.85
200
C
RSS
C
OSS
0.75
-40
0
40
80
120
160
0
T
J
, JUNCTION TEMPERATURE (
o
C)
10
20
30
40
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
50
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
5
I
SD
, SOURCE TO DRAIN CURRENT (A)
80µs PULSE TEST
g
fs
, TRANSCONDUCTANCE (S)
4
T
J
= -55
o
C
T
J
= 25
o
C
3
T
J
= 125
o
C
2
10
2
T
J
= 25
o
C
T
J
= 150
o
C
10
T
J
= 150
o
C
1
T
J
= 25
o
C
1
0
2
1
3
V
SD
, SOURCE TO DRAIN VOLTAGE (V)
4
0
0
2
4
6
I
D
, DRAIN CURRENT (A)
8
10
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT
FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
20
V
GS
, GATE TO SOURCE VOLTAGE (V)
I
D
= 3.5A
V
DS
= 40V
V
DS
= 100V
V
DS
= 160V
15
10
5
0
0
4
8
12
16
20
Q
g(TOT)
, TOTAL GATE CHARGE (nC)
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
©2001 Fairchild Semiconductor Corporation
IRFF220 Rev. A
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