82C54
CHMOS PROGRAMMABLE INTERVAL TIMER
Y
Compatible with all Intel and most
other microprocessors
High Speed ‘‘Zero Wait State’’
Operation with 8 MHz 8086 88 and
80186 188
Handles Inputs from DC
10 MHz for 82C54-2
Available in EXPRESS
Standard Temperature Range
Extended Temperature Range
Y
Y
Three independent 16-bit counters
Low Power CHMOS
I
CC
e
10 mA
8 MHz Count
frequency
Completely TTL Compatible
Six Programmable Counter Modes
Binary or BCD counting
Status Read Back Command
Available in 24-Pin DIP and 28-Pin PLCC
Y
Y
Y
Y
Y
Y
Y
Y
The Intel 82C54 is a high-performance CHMOS version of the industry standard 8254 counter timer which is
designed to solve the timing control problems common in microcomputer system design It provides three
independent 16-bit counters each capable of handling clock inputs up to 10 MHz All modes are software
programmable The 82C54 is pin compatible with the HMOS 8254 and is a superset of the 8253
Six programmable timer modes allow the 82C54 to be used as an event counter elapsed time indicator
programmable one-shot and in many other applications
The 82C54 is fabricated on Intel’s advanced CHMOS III technology which provides low power consumption
with performance equal to or greater than the equivalent HMOS product The 82C54 is available in 24-pin DIP
and 28-pin plastic leaded chip carrier (PLCC) packages
231244 – 3
PLASTIC LEADED CHIP CARRIER
231244 – 1
Figure 1 82C54 Block Diagram
231244 – 2
Diagrams are for pin reference only
Package sizes are not to scale
Figure 2 82C54 Pinout
October 1994
Order Number 231244-006
82C54
Table 1 Pin Description
Symbol
DIP
D
7
-D
0
CLK 0
OUT 0
GATE 0
GND
OUT 1
GATE 1
CLK 1
GATE 2
OUT 2
CLK 2
A
1
A
0
1-8
9
10
11
12
13
14
15
16
17
18
20-19
Pin Number
PLCC
2-9
10
12
13
14
16
17
18
19
20
21
23-22
I O
I
O
I
O
I
I
I
O
I
I
Data Bidirectional tri-state data bus lines
connected to system data bus
Clock 0 Clock input of Counter 0
Output 0 Output of Counter 0
Gate 0 Gate input of Counter 0
Ground Power supply connection
Out 1 Output of Counter 1
Gate 1 Gate input of Counter 1
Clock 1 Clock input of Counter 1
Gate 2 Gate input of Counter 2
Out 2 Output of Counter 2
Clock 2 Clock input of Counter 2
Address Used to select one of the three Counters
or the Control Word Register for read or write
operations Normally connected to the system
address bus
A
1
0
0
1
1
CS
21
24
I
A
0
0
1
0
1
Selects
Counter 0
Counter 1
Counter 2
Control Word Register
Type
Function
RD
WR
V
CC
NC
22
23
24
26
27
28
1 11 15 25
I
I
Chip Select A low on this input enables the 82C54
to respond to RD and WR signals RD and WR are
ignored otherwise
Read Control This input is low during CPU read
operations
Write Control This input is low during CPU write
operations
Power
a
5V power supply connection
No Connect
sired delay After the desired delay the 82C54 will
interrupt the CPU Software overhead is minimal and
variable length delays can easily be accommodated
Some of the other counter timer functions common
to microcomputers which can be implemented with
the 82C54 are
FUNCTIONAL DESCRIPTION
General
The 82C54 is a programmable interval timer counter
designed for use with Intel microcomputer systems
It is a general purpose multi-timing element that can
be treated as an array of I O ports in the system
software
The 82C54 solves one of the most common prob-
lems in any microcomputer system the generation
of accurate time delays under software control In-
stead of setting up timing loops in software the pro-
grammer configures the 82C54 to match his require-
ments and programs one of the counters for the de-
2
Real time clock
Even counter
Digital one-shot
Programmable rate generator
Square wave generator
Binary rate multiplier
Complex waveform generator
Complex motor controller
82C54
Block Diagram
DATA BUS BUFFER
This 3-state bi-directional 8-bit buffer is used to in-
terface the 82C54 to the system bus (see Figure 3)
CONTROL WORD REGISTER
The Control Word Register (see Figure 4) is selected
by the Read Write Logic when A
1
A
0
e
11 If the
CPU then does a write operation to the 82C54 the
data is stored in the Control Word Register and is
interpreted as a Control Word used to define the
operation of the Counters
The Control Word Register can only be written to
status information is available with the Read-Back
Command
231244 – 4
Figure 3 Block Diagram Showing Data Bus
Buffer and Read Write Logic Functions
231244 – 5
READ WRITE LOGIC
The Read Write Logic accepts inputs from the sys-
tem bus and generates control signals for the other
functional blocks of the 82C54 A
1
and A
0
select
one of the three counters or the Control Word Regis-
ter to be read from written into A ‘‘low’’ on the RD
input tells the 82C54 that the CPU is reading one of
the counters A ‘‘low’’ on the WR input tells the
82C54 that the CPU is writing either a Control Word
or an initial count Both RD and WR are qualified by
CS RD and WR are ignored unless the 82C54 has
been selected by holding CS low
The WR and CLK signals should be synchronous
This is accomplished by using a CLK input signal to
the 82C54 counters which is a derivative of the sys-
tem clock source Another technique is to externally
synchronize the WR and CLK input signals This is
done by gating WR with CLK
Figure 4 Block Diagram Showing Control Word
Register and Counter Functions
COUNTER 0 COUNTER 1 COUNTER 2
These three functional blocks are identical in opera-
tion so only a single Counter will be described The
internal block diagram of a single counter is shown
in Figure 5
The Counters are fully independent Each Counter
may operate in a different Mode
The Control Word Register is shown in the figure it
is not part of the Counter itself but its contents de-
termine how the Counter operates
3
82C54
stored in the CR and later transferred to the CE The
Control Logic allows one register at a time to be
loaded from the internal bus Both bytes are trans-
ferred to the CE simultaneously CR
M
and CR
L
are
cleared when the Counter is programmed In this
way if the Counter has been programmed for one
byte counts (either most significant byte only or least
significant byte only) the other byte will be zero
Note that the CE cannot be written into whenever a
count is written it is written into the CR
The Control Logic is also shown in the diagram CLK
n GATE n and OUT n are all connected to the out-
side world through the Control Logic
82C54 SYSTEM INTERFACE
231244 – 6
Figure 5 Internal Block Diagram of a Counter
The status register shown in the Figure when
latched contains the current contents of the Control
Word Register and status of the output and null
count flag (See detailed explanation of the Read-
Back command )
The actual counter is labelled CE (for ‘‘Counting Ele-
ment’’) It is a 16-bit presettable synchronous down
counter
OL
M
and OL
L
are two 8-bit latches OL stands for
‘‘Output Latch’’ the subscripts M and L stand for
‘‘Most significant byte’’ and ‘‘Least significant byte’’
respectively Both are normally referred to as one
unit and called just OL These latches normally ‘‘fol-
low’’ the CE but if a suitable Counter Latch Com-
mand is sent to the 82C54 the latches ‘‘latch’’ the
present count until read by the CPU and then return
to ‘‘following’’ the CE One latch at a time is enabled
by the counter’s Control Logic to drive the internal
bus This is how the 16-bit Counter communicates
over the 8-bit internal bus Note that the CE itself
cannot be read whenever you read the count it is
the OL that is being read
Similarly there are two 8-bit registers called CR
M
and CR
L
(for ‘‘Count Register’’) Both are normally
referred to as one unit and called just CR When a
new count is written to the Counter the count is
The 82C54 is treated by the systems software as an
array of peripheral I O ports three are counters and
the fourth is a control register for MODE program-
ming
Basically the select inputs A
0
A
1
connect to the A
0
A
1
address bus signals of the CPU The CS can be
derived directly from the address bus using a linear
select method Or it can be connected to the output
of a decoder such as an Intel 8205 for larger sys-
tems
231244 – 7
Figure 6 82C54 System Interface
4
82C54
OPERATIONAL DESCRIPTION
General
After power-up the state of the 82C54 is undefined
The Mode count value and output of all Counters
are undefined
How each Counter operates is determined when it is
programmed Each Counter must be programmed
before it can be used Unused counters need not be
programmed
Programming the 82C54
Counters are programmed by writing a Control Word
and then an initial count The control word format is
shown in Figure 7
All Control Words are written into the Control Word
Register which is selected when A
1
A
0
e
11 The
Control Word itself specifies which Counter is being
programmed
By contrast initial counts are written into the Coun-
ters not the Control Word Register The A
1
A
0
in-
puts are used to select the Counter to be written
into The format of the initial count is determined by
the Control Word used
Control Word Format
A
1
A
0
e
11
CS
e
0 RD
e
1 WR
e
0
D
7
SC1
SC
Select Counter
SC1
SC0
0
0
1
1
0
1
0
1
Select Counter 0
Select Counter 1
Select Counter 2
Read-Back Command
(See Read Operations)
D
6
SC0
D
5
RW1
D
4
RW0
D
3
M2
M
D
2
M1
D
1
M0
D
0
BCD
MODE
M2
0
0
X
X
1
1
M1
0
0
1
1
0
0
M0
0
1
0
1
0
1
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
RW
Read Write
RW1 RW0
0
0
1
1
0
1
0
1
Counter Latch Command (see Read
Operations)
Read Write least significant byte only
Read Write most significant byte only
Read Write least significant byte first
then most significant byte
BCD
0
1
Binary Counter 16-bits
Binary Coded Decimal (BCD) Counter
(4 Decades)
NOTE
Don’t care bits (X) should be 0 to insure
compatibility with future Intel products
Figure 7 Control Word Format
5
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