a
FEATURES
Single Chip Construction
On-Board Output Amplifier
Low Power Dissipation: 300 mW
Monotonicity Guaranteed over Temperature
Guaranteed for Operation with 12 V Supplies
Improved Replacement for Standard DAC80, DAC800
Hl-5680
High Stability, High Current Output
Buried Zener Reference
Laser Trimmed to High Accuracy
1/2 LSB Max Nonlinearity
Low Cost Plastic Packaging
Complete Low Cost
12-Bit D/A Converters
ADDAC80/ADDAC85/ADDAC87
FUNCTIONAL BLOCK DIAGRAM
(MSB) BIT 1
1
BIT 2
2
24
V
REF
OUT
GAIN ADJUST
+V
S
COMMON
SUMMING JUNCTION
20V RANGE
10V RANGE
BIPOLAR OFFSET
REF INPUT
V
OUT
BIT 3
3
BIT 4
4
BIT 5
5
BIT 6
6
BIT 7
7
BIT 8
8
REF
CONTROL
CIRCUIT
12-BIT
RESISTOR
LADDER
NETWORK
AND
CURRENT
SWITCHES
23
22
21
20
5k
5k
19
18
17
16
15
14
13
PRODUCT DESCRIPTION
The ADDAC80 Series is a family of low cost 12-bit digital-to-
analog converters with both a high stability voltage reference
and output amplifier combined on a single monolithic chip.
The ADDAC80 Series is recommended for all low cost 12-bit D/A
converter applications where reliability and cost are of paramount
importance.
Advanced circuit design and precision processing techniques
result in significant performance advantages over conventional
DAC80 devices. Innovative circuit design reduces the total
power consumption to 300 mW, which not only improves reli-
ability, but also improves long term stability.
LE
(MSB) BIT 1
1
BIT 2
2
BIT 3
3
BIT 4
4
BIT 5
5
SO
The ADDAC80 incorporates a fully differential, nonsaturating
precision current switching cell structure which provides greatly
increased immunity to supply voltage variation. This same struc-
ture also reduces nonlinearities due to thermal transients as the
various bits are switched; nearly all critical components operate
at constant power dissipation. High stability, SiCr thin film
resistors are trimmed with a fine resolution laser, resulting in
lower differential nonlinearity errors. A low noise, high stability,
subsurface Zener diode is used to produce a reference voltage
with excellent long term stability, high external current capabil-
ity and temperature drift characteristics which challenge the
best discrete Zener references.
B
PRODUCT HIGHLIGHTS
1. The ADDAC80 series of D/A converters directly replaces all
other devices of this type with significant increases in performance.
2. Single chip construction and low power consumption pro-
vides the optimum choice for applications where low cost
and high reliability are major considerations.
3. The high speed output amplifier has been designed to settle
within 1/2 LSB for a 10 V full scale transition in 2.0
µs,
when
properly compensated.
4. The precision buried Zener reference can supply up to 2.5 mA
for use elsewhere in the application.
5. The low TC binary ladder guarantees that all units are mono-
tonic over the specified temperature range.
6. System performance upgrading is possible without redesign.
The ADDAC80 Series is available in three performance grades
and three package types. The ADDAC80 is specified for use
over the 0°C to 70°C temperature range and is available in
both plastic and ceramic DIP packages. The ADDAC85 and
ADDAC87 are available in hermetically sealed ceramic packages
and are specified for the –25°C to +85°C and –55°C to +125°C
temperature ranges.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
O
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
TE
BIT 9
9
6.3k
BIT 10
10
BIT 11
11
–
+
(LSB) BIT 12
12
–V
S
NC/+V
L
*
ADDAC80
*NC
= CBI VERSIONS
5V – CCD VERSIONS
24
V
REF
OUT
REF
CONTROL
CIRCUIT
23
GAIN ADJUST
22
+V
S
21
COMMON
20
SCALING NETWORK
BIT 6
6
BIT 7
7
BIT 8
8
BIT 9
9
12-BIT
RESISTOR
LADDER
NETWORK
AND
CURRENT
SWITCHES
2k
5k
5k
6.3k
19
SCALING NETWORK
18
SCALING NETWORK
17
BIPOLAR OFFSET
16
REF INPUT
15
I
OUT
14
–V
S
13
NC/+V
L
*
BIT 10
10
BIT 11
11
(LSB) BIT 12
12
*NC
= CBI VERSIONS
5V – CCD VERSIONS
ADDAC80/ADDAC85/ADDAC87–SPECIFICATIONS
Model
TECHNOLOGY
DIGITAL INPUT
Binary–CBI
BCD–CCD
Logic Levels (TTL Compatible)
V
IH
(Logic “1”)
V
IL
(Logic “0”)
I
IH
(V
IH
= 5.5 V)
I
IL
(V
IL
= 0.8 V)
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error @ 25°C
CBI
CCD
T
A
@ T
MIN
to T
MAX
Differential Linearity Error @ 25°C
CBI
CCD
T
A
@ T
MIN
to T
MAX
Gain Error
2
Offset Error
2
Temperature Range for Guaranteed
Monotonicity
DRIFT (T
MIN
to T
MAX
)
Total Bipolar Drift, max (includes gain,
offset, and linearity drifts)
Total Error (T
MIN
to T
MAX
)
4
Unipolar
Bipolar
Gain Including Internal Reference
Gain Excluding Internal Reference
Unipolar Offset
Bipolar Offset
CONVERSION SPEED
Voltage Model (V)
5
Settling Time to
±
0.01% of FSR for
FSR Change (2 kΩ 500 pF load)
with 10 kΩ Feedback
with 5 kΩ Feedback
For LSB Change
Slew Rate
ANALOG OUTPUT
Voltage Models
Ranges–CBI
Min
ADDAC80
Typ
Max
Monolithic
12
2.0
0
5.5
0.8
250
100
2.0
0
Min
ADDAC85
Typ
Max
Monolithic
12
5.5
0.8
250
100
2.0
0
Min
(T
A
= 25 C, rated power supplies
unless otherwise noted.)
ADDAC87
Typ
Max
Monolithic
12
5.5
0.8
250
100
Bits
Digits
V
V
µA
µA
Unit
±
1/2
±
1/4
±
1/2
±
1/4
±
1/2
±
1/2
±
3/4
±
0.1
±
0.05
0
TE
±
3/4
±
3/4
±
1
±
0.2
±
0.1
±
0.1
±
0.05
±
1/2
±
1/2
±
3/4
LSB
1
LSB
LSB
LSB
LSB
LSB
%FSR
3
%FSR
3
°C
±
3/4
±
0.3
±
0.15
+70
±
20
–25
±
0.1
±
0.05
±
1
±
0.2
±
0.1
+85
–55
+125
LE
±
20
±
0.15
±
0.10
±
30
±
7
±
3
±
10
±
0.12
±
0.08
±
0.2
±
0.12
±
20
±
10
±
3
±
10
4
3
3
2
1
4
3
10
10
±2.5, ±5,
±
10, +5,
10
±
5
±
5
0.05
40
6.37
2.5
±
20
0.002
0.002
6.23
6.3
1.5
±
10
40
6.37
2.5
±
20
0.002
0.002
±
15
±
16.5
±
11.4
7
5
14
±
16.5
10
20
±
11.4
7
6.23
10
20
±
30
±
0.18
±
0.14
±
0.3
±
0.24
±
20
±
10
±
3
±
10
ppm of FSR/°C
% of FSR
% of FSR
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
SO
3
2
1
10
±2.5, ±5,
±
10, +5,
10
0.05
6.23
6.3
1.5
±
10
±
5
±
15
±
11.4
7
5
14
±
0.08
±
0.06
±
15
±
4
±
1
±
5
3
2
1
4
3
µs
µs
µs
V/µs
B
±
2.5,
±
5,
±
10, +5,
10
0.05
6.3
1.5
40
6.37
2.5
±
10
0.002
0.002
±
15
±
16.5
5
14
10
20
–CCD
Output Current
Output Impedance (dc)
Short Circuit Current
Internal Reference Voltage (V
R
)
Output Impedance
Max External Current
6
Tempco of Drift
V
V
V
V
mA
Ω
mA
V
Ω
mA
ppm of V
R
/°C
% of FSR/%V
S
% of FSR/%V
S
V
V
V
mA
mA
POWER SUPPLY SENSITIVITY
±
15 V
±
10%, 5 V supply when applicable
±
12 V
±
5%
POWER SUPPLY REQUIREMENTS
Rated Voltages
Range
Analog Supplies
Logic Supplies
Supply Drain
+12 V, +15 V
–12 V, –15 V
O
–2–
REV. B
ADDAC80/ADDAC85/ADDAC87
Model
TEMPERATURE RANGE
Specifications
Operating
Storage
Min
0
–25
–25
ADDAC80
Typ
Max
+70
+85
+125
Min
–25
–55
–65
ADDAC85
Typ
Max
+85
+125
+150
Min
–55
–55
–65
ADDAC87
Typ
Max
+125
+125
+150
Unit
°C
°C
°C
NOTES
1
Least Significant Bit.
2
Adjustable to zero with external trim potentiometer.
3
FSR means “Full Scale Range” and is 20 V for the
±
10 V range and 10 V for the
±
5 V range.
4
Gain and offset errors adjusted to zero at 25°C.
5
C
F
= 0, see Figure 3a.
6
Maximum with no degradation of specification, must be a constant load.
7
A minimum of
±
12.3 V is required for a
±
10 V full scale output and
±
11.4 V is required for all other voltage ranges.
Specifications shown in
boldface
are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
Specifications subject to change without notice.
Model
TECHNOLOGY
DIGITAL INPUT
Binary–CBI
BCD–CCD
Logic Levels (TTL Compatible)
V
IH
(Logic “1”)
V
IL
(Logic “0”)
I
IH
(V
IH
= 5.5 V)
I
IL
(V
IL
= 0.8 V)
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error @ 25°C
CBI
CCD
T
A
@ T
MIN
to T
MAX
Differential Linearity Error @ 25°C
CBI
CCD
T
A
@ T
MIN
to T
MAX
Gain Error
2
Offset Error
2
Temperature Range for Guaranteed
Monotonicity
DRIFT (T
MIN
to T
MAX
)
Total Bipolar Drift, max (includes gain,
offset, and linearity drifts)
Total Error (T
MIN
to T
MAX
)
4
Unipolar
Bipolar
Gain
Including Internal Reference
Excluding Internal Reference
Unipolar Offset
Bipolar Offset
Min
ADDAC80
Typ
Max
Hybrid
12
3
Min
ADDAC85
Typ
Max
Hybrid
TE
Min
ADDAC87
Typ
Max
Hybrid
12
3
12
3
5.5
0.8
2.0
0
250
–100
5.5
0.8
250
–100
±
1/4
±
1/2
±
1/2
±
0.1
±
0.05
±
1/2
±
1/4
±
1/2
±
1/2
±
1/2
±
1/2
±
0.1
±
0.05
–25
±
1/2
±
1/4
±
1/2
±
1
±
1
+70
+85
±
1
±
20
±
10
±
10
±
1
±
20
±
10
±
10
5
3
1.5
20
5
3
1.5
20
300
1
300
1
Unit
2.0
0
LE
5.5
0.8
2.0
0
±
1/2
±
1/4
±
1/2
±
3/4
±
1/2
±
1
±
0.3
±
0.15
+70
±
20
0
±
0.15
±
0.10
±
30
±
7
±
3
±
10
Bits
Digits
V
V
µA
µA
250
–100
SO
±
1/4
±
1/8
±
1/4
±
1/2
±
1/4
±
0.1
±
0.05
0
±
0.08
±
0.06
±
15
±
5
±
1
±
5
10
5
3
1.5
15
300
1
LSB
1
LSB
LSB
LSB
LSB
LSB
%FSR
3
%FSR
3
°C
ppm of FSR/°C
% of FSR
% of FSR
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
CONVERSION SPEED
Voltage Model (V)
5
Settling Time to
±
0.01% of FSR for
FSR Change (2 kΩ 500 pF load)
with 10 kΩ Feedback
with 5 kΩ Feedback
For LSB Change
Slew Rate
Current Model (I)
Settling time to
±
0.01% of FSR for
FSR Change
10
Ω
to 100
Ω
Load
for 1 kΩ
O
B
µs
µs
µs
V/µs
ns
µs
REV. B
–3–
ADDAC80/ADDAC85/ADDAC87–SPECIFICATIONS
(continued)
Model
ANALOG OUTPUT
Voltage Models
Ranges–CBI
Ranges–CCD
Output Current
Output Impedance (dc)
Short Circuit Duration
Current Models
Ranges–Unipolar
Ranges–Bipolar
Output Impedance
Bipolar
Unipolar
Compliance
Internal Reference Voltage (V
R
)
Output Impedance
Max External Current
6
Tempco of Drift
POWER SUPPLY SENSITIVITY
±
15 V
±
10%, 5 V Supply When Applicable
POWER SUPPLY REQUIREMENTS
Rated Voltages
Range
Analog Supplies
Logic Supplies
Supply Drain
7
+15 V
–15 V
+5 V
8
TEMPERATURE RANGE
Specifications
Operating
Storage
Min
ADDAC80
Typ
Max
Min
ADDAC85
Typ
Max
Min
ADDAC87
Typ
Max
Unit
±
2.5,
±
5,
±
10, +5,
+10
±
10
±
2.5,
±
5,
±
10, +5,
+10
+10
±
2.5,
±
5,
±
10, +5,
+10
+10
±
5
±
5
±
5
0.05
Indefinite to Common
–2.0
±
1.0
3.2
6.6
–1.5, +10
6.3
6.43
1.5
2.5
±
10
±
20
±
0.002
±
15, +5
±
14
4.5
10
20
8
0
–25
–55
0.05
Indefinite to Common
–2.0
±
1.0
3.2
6.6
–2.5, +10
6.3
6.43
1.5
2.5
±
10
±
20
±
0.002
0.05
Indefinite to Common
–2.0
±
1.0
3.2
6.6
–2.5, +10
6.3
6.43
1.5
2.5
±
10
±
20
±
0.002
V
V
mA
Ω
mA
mA
kΩ
kΩ
V
V
Ω
mA
ppm of V
R
/°C
% of FSR/%V
S
V
V
V
mA
mA
mA
°C
°C
°C
6.17
6.17
LE
±
16
16
20
35
20
±
14.5
4.5
±
15.5
15.5
20
30
20
15
25
15
+70
+85
+130
0
–25
–65
+70
+85
+150
–25
–55
–65
±
15, +5
SO
–4–
Specifications subject to change without notice.
O
B
NOTES
1
Least Significant Bit.
2
Adjustable to zero with external trim potentiometer.
3
FSR means “Full Scale Range” and is 20 V for the
±
10 V range and 10 V for the
±
5 V range.
4
Gain and offset errors adjusted to zero at 25°C.
5
C
F
= 0, see Figure 3a.
6
Maximum with no degradation of specification, must be a constant load.
7
Including 5 mA load.
8
5 V supply required only for CCD versions.
TE
6.17
±
15, +5
±
14.5
4.5
15
25
15
±
15.5
15.5
20
30
20
+85
+125
+150
REV. B
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