CS4297A datasheet, PDF - EEWORLD Datasheet

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CS4297A: DescriptionSPECIALTY CONSUMER CIRCUIT, PQFP48; Categorysemiconductor Other integrated circuit (IC); File Size1MB，66 Pages; ManufacturerCirrus Logic; Websitehttp://www.cirrus.com

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CS4297A Overview

SPECIALTY CONSUMER CIRCUIT, PQFP48

CS4297A Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	48
Maximum operating temperature	70 Cel
Minimum operating temperature	0.0 Cel
Maximum supply/operating voltage	5.25 V
Minimum supply/operating voltage	4.75 V
Processing package description	9 X 9 MM, 1.40 MM HEIGHT, LEAD FREE, MS-022, TQFP-48
Lead-free	Yes
EU RoHS regulations	Yes
state	ACTIVE
packaging shape	SQUARE
Package Size	FLATPACK, LOW PROFILE, FINE PITCH
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.5000 mm
terminal coating	MATTE TIN
Terminal location	QUAD
Packaging Materials	PLASTIC/EPOXY
Temperature level	COMMERCIAL
Consumer IC Type	CONSUMER CIRCUIT

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CS4202

Audio Codec ’97 with Headphone Amplifier

Features

Sample

’97 2.2 Compliant

Exceeds

the Microsoft

PC 2001 Audio

Performance Requirements

High-Performance Headphone

Amplifier

Integrated

On-chip

PLL for use with External Clock

Rate Converters

Three Analog Line-level Stereo Inputs

High Quality Pseudo-Differential CD Input

Two Analog Line-level Mono Inputs

Dual Microphone Inputs

Stereo and Mono Line-level Outputs

Extensive Power Management Support

Sources

Integrated

Automatic

Description

The CS4202 is an AC ’97 2.2 compliant stereo audio co-

dec designed for PC multimedia systems. It uses

industry leading delta-sigma and mixed signal technolo-

gy. This advanced technology and these features are

designed to help enable the design of PC 99 and

PC 2001 compliant high-quality audio systems for desk-

top, portable, and entertainment PCs.

Coupling the CS4202 with a PCI audio accelerator or

core logic supporting the AC ’97 interface implements a

cost effective, superior quality audio solution. The

CS4202 surpasses PC 99, PC 2001, and AC ’97 2.2 au-

dio quality standards.

ORDERING INFO

CS4202-JQZ, Lead Free 48-pin TQFP 9x9x1.4 mm

High-Performance Microphone

Pre-Amplifier

Jack Sense through GPIO

Interface for Audio Feature

Configuration through Software

BIOS-Driver

S/PDIF Digital Audio Output

S Serial Digital Outputs Enable

Independent

20-bit

18-bit

Cost

Effective Six Channel Applications

Simultaneous S/PDIF and Six

Channel Audio Playback

Stereo Digital-to-Analog Converters

Stereo Analog-to-Digital Converters

AC-LINK AND AC '97

REGISTERS

ANALOG INPUT MUX

AND OUTPUT MIXER

TEST

PWR

MGT

SRC

LINE

PCM_DATA

18 bit

ADC

INPUT

MUX

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

RESET#

ID0#

ID1#

AC-

LINK

AUX

VIDEO

MIC1

MIC2

PHONE

PC_BEEP

INPUT

MIXER

GAIN / MUTE CONTROLS

MIXER / MUX SELECTS

AC '97

REGISTERS

OUTPUT

MIXER

EAPD

SPDIF_OUT

GPIO[4:0]

SDOUT,LRCLK,SCLK

GPIO, S/PDIF

SERIAL DATA PORT

SRC

LINE_OUT

HP_OUT

MONO_OUT

PCM_DATA

20 bit

DAC

Preliminary Product Information

http://www.cirrus.com

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

Cirrus Logic, Inc. 2005

JULY '05

DS549PP2

CS4202

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 7

ANALOG CHARACTERISTICS ................................................................................................ 7

ABSOLUTE MAXIMUM RATINGS ........................................................................................... 8

RECOMMENDED OPERATING CONDITIONS ....................................................................... 8

AC ’97 SERIAL PORT TIMING............................................................................................... 10

2. GENERAL DESCRIPTION ..................................................................................................... 13

2.1 AC-Link ............................................................................................................................ 13

2.2 Control Registers ............................................................................................................. 14

2.3 Sample Rate Converters .................................................................................................. 14

2.4 Mixers .............................................................................................................................. 14

2.5 Input Mux ......................................................................................................................... 14

2.6 Volume Control ................................................................................................................ 14

3. AC-LINK FRAME DEFINITION .............................................................................................. 16

3.1 AC-Link Serial Data Output Frame .................................................................................. 17

3.1.1 Serial Data Output Slot Tags (Slot 0)............................................................................. 17

3.1.2 Command Address Port (Slot 1) .................................................................................... 17

3.1.3 Command Data Port (Slot 2).......................................................................................... 18

3.1.4 PCM Playback Data (Slots 3-4,6-11) ............................................................................. 18

3.1.5 GPIO Pin Control (Slot12).............................................................................................. 18

3.2 AC-Link Serial Data Input Frame ..................................................................................... 19

3.2.1 Serial Data Input Slot Tag Bits (Slot 0) ........................................................................ 19

3.2.2 Status Address Port (Slot 1) .......................................................................................... 19

3.2.3 Status Data Port (Slot 2) ................................................................................................ 20

3.2.4 PCM Capture Data (Slot 3-4,6-8,11).............................................................................. 20

3.2.5 GPIO Pin Status (Slot 12) ............................................................................................. 20

3.3 AC-Link Protocol Violation - Loss of SYNC ..................................................................... 21

4. REGISTER INTERFACE ..................................................................................................... 22

4.1 Reset Register (Index 00h) .............................................................................................. 23

4.2 Analog Mixer Output Volume Registers (Index 02h - 04h) .............................................. 23

4.3 Mono Volume Register (Index 06h) .................................................................................. 24

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/sales.cfm

IMPORTANT NOTICE

"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its

subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without

notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to

verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied

at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for

the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of

third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask

work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained here-

in and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of

Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for

resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE

PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED

FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SE-

CURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS

IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IM-

PLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS

PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PROD-

UCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES,

DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR

ARISE IN CONNECTION WITH THESE USES.

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade-

marks or service marks of their respective owners.

DS549PP2

CS4202

4.4 PC_BEEP Volume Register (Index 0Ah) .......................................................................... 24

4.5 Phone Volume Register (Index 0Ch) ................................................................................ 24

4.6 Microphone Volume Register (Index 0Eh)........................................................................ 25

4.7 Analog Mixer Input Gain Registers (Index 10h - 18h) ...................................................... 26

4.8 Input Mux Select Register (Index 1Ah) ............................................................................. 27

4.9 Record Gain Register (Index 1Ch) ................................................................................... 28

4.10 General Purpose Register (Index 20h) ......................................................................... 29

4.11 Powerdown Control/Status Register (Index 26h) ........................................................... 30

4.12 Extended Audio ID Register (Index 28h) ........................................................................ 31

4.13 Extended Audio Status/Control Register (Index 2Ah) .................................................... 32

4.14 Audio Sample Rate Control Registers (Index 2Ch - 32h) ............................................... 33

4.15 S/PDIF Control Register (Index 3Ah) ............................................................................. 34

4.16 Extended Modem ID Register (Index 3Ch) .................................................................... 35

4.17 Extended Modem Status/Control Register (Index 3Eh) ................................................. 35

4.18 GPIO Pin Configuration Register (Index 4Ch) ................................................................ 35

4.19 GPIO Pin Polarity/Type Configuration Register (Index 4Eh) .......................................... 36

4.20 GPIO Pin Sticky Register (Index 50h) ............................................................................ 36

4.21 GPIO Pin Wakeup Mask Register (Index 52h) ............................................................... 37

4.22 GPIO Pin Status Register (Index 54h)............................................................................ 37

4.23 AC Mode Control Register (Index 5Eh) .......................................................................... 37

4.24 Misc. Crystal Control Register (Index 60h) ..................................................................... 39

4.25 Serial Port Control Register (Index 6Ah) ........................................................................ 40

4.26 BIOS-Driver Interface Control Registers (Index 70h - 72h) ............................................ 41

4.27 BIOS-Driver Interface Status Register (Index 7Ah) ........................................................ 41

4.28 Vendor ID1 Register (Index 7Ch) ................................................................................... 42

4.29 Vendor ID2 Register (Index 7Eh) ................................................................................... 42

5. SERIAL DATA PORTS ........................................................................................................... 43

5.1 Overview .......................................................................................................................... 43

5.2 Multi-Channel Expansion ................................................................................................. 43

5.3 Serial Data Formats ......................................................................................................... 44

6. SONY/PHILIPS DIGITAL INTERFACE (S/PDIF) ................................................................... 45

7. EXCLUSIVE FUNCTIONS ...................................................................................................... 45

8. POWER MANAGEMENT ....................................................................................................... 46

8.1 AC ’97 Reset Modes ........................................................................................................ 46

8.1.1 Cold Reset .......................................................................................................... 46

8.1.2 Warm Reset ........................................................................................................ 46

8.1.3 New Warm Reset ................................................................................................ 46

8.1.4 Register Reset .................................................................................................... 46

8.2 Powerdown Controls ....................................................................................................... 47

9. CLOCKING ............................................................................................................................. 49

9.1 PLL Operation (External Clock) ....................................................................................... 49

9.2 24.576 MHz Crystal Operation ........................................................................................ 49

9.3 Secondary Codec Operation ........................................................................................... 49

10. ANALOG HARDWARE DESCRIPTION ............................................................................... 51

10.1 Analog Inputs ................................................................................................................. 51

10.1.1 Line Inputs ........................................................................................................ 51

10.1.2 CD Input ............................................................................................................ 51

10.1.3 Microphone Inputs ............................................................................................ 51

10.1.4 PC Beep Input ................................................................................................... 52

10.1.5 Phone Input ....................................................................................................... 52

10.2 Analog Outputs .............................................................................................................. 52

10.2.1 Stereo Outputs .................................................................................................. 52

10.2.2 Mono Output ..................................................................................................... 53

10.3 Miscellaneous Analog Signals ....................................................................................... 53

DS549PP2

CS4202

10.4 Power Supplies .............................................................................................................. 53

10.5 Reference Design .......................................................................................................... 53

11. GROUNDING AND LAYOUT .............................................................................................. 54

12. PIN DESCRIPTIONS

14. REFERENCE DESIGN

........................................................................................................ 56

................................................................................................... 64

13. PARAMETER AND TERM DEFINITIONS ............................................................................ 62

15. REFERENCES ...................................................................................................................... 65

16. PACKAGE DIMENSIONS ..................................................................................................... 66

LIST OF FIGURES

Figure 1. Power Up Timing............................................................................................................ 11

Figure 2. Codec Ready from Start-up or Fault Condition .............................................................. 11

Figure 3. Clocks ............................................................................................................................ 11

Figure 4. Data Setup and Hold...................................................................................................... 12

Figure 5. PR4 Powerdown and Warm Reset ................................................................................ 12

Figure 6. Test Mode ...................................................................................................................... 12

Figure 7. AC-link Connections....................................................................................................... 13

Figure 8. CS4202 Mixer Diagram.................................................................................................. 15

Figure 9. AC-link Input and Output Framing.................................................................................. 16

Figure 10. Serial Data Port: Six Channel Circuit ........................................................................... 43

Figure 11. Serial Data Format 0 (I2S) ........................................................................................... 44

Figure 12. Serial Data Format 1 (Left Justified) ............................................................................ 44

Figure 13. Serial Data Format 2 (Right Justified, 20-bit data) ....................................................... 44

Figure 14. Serial Data Format 3 (Right Justified, 16-bit data) ....................................................... 44

Figure 15. S/PDIF Output.............................................................................................................. 45

Figure 16. PLL External Loop Filter............................................................................................... 49

Figure 17. External Crystal............................................................................................................ 50

Figure 18. Line Input (Replicate for Video and AUX) .................................................................... 51

Figure 19. Differential 1 VRMS CD Input ...................................................................................... 51

Figure 20. Microphone Input ......................................................................................................... 52

Figure 21. PC_BEEP Input............................................................................................................ 52

Figure 22. Modem Connection ...................................................................................................... 52

Figure 23. Line Out and Headphone Out Setup............................................................................ 53

Figure 24. Line Out/Headphone Out Setup................................................................................... 53

Figure 25. +5V Analog Voltage Regulator..................................................................................... 54

Figure 26. Conceptual Layout for the CS4202 when in XTAL or OSC Clocking Modes ............... 55

Figure 27. Pin Locations for the CS4202 ...................................................................................... 56

Figure 28. CS4202 Reference Design .......................................................................................... 64

DS549PP2

CS4202

LIST OF TABLES

Table 1. Register Overview for the CS4202 ..................................................................... 22

Table 2. Analog Mixer Output Attenuation........................................................................ 23

Table 3. Microphone Input Gain Values ........................................................................... 25

Table 4. Analog Mixer Input Gain Values ......................................................................... 26

Table 5. Analog Mixer Input Gain Register Index ............................................................. 26

Table 6. Input Mux Selection ............................................................................................ 27

Table 7. Record Gain Values ........................................................................................... 28

Table 8. Slot Mapping for the CS4202 ............................................................................. 31

Table 9. Slot Assignment Defaults ................................................................................... 31

Table 10. Directly Supported SRC Sample Rates for the CS4202................................... 33

Table 11. GPIO Input/Output Configurations.................................................................... 36

Table 12. Serial Data Format Selection............................................................................ 40

Table 13. Device ID with Corresponding Part Number..................................................... 42

Table 14. Serial Data Formats and Compatible DACs for the CS4202 ............................ 44

Table 15. Powerdown PR Bit Functions ........................................................................... 47

Table 16. Powerdown PR Function Matrix for the CS4202 .............................................. 48

Table 17. Power Consumption by Powerdown Mode for the CS4202 ............................. 48

Table 18. Clocking Configurations for the CS4202 .......................................................... 50

DS549PP2

CS4297A Related Products

	CS4297A	CS4294/CS4298	CS4297
Description	SPECIALTY CONSUMER CIRCUIT, PQFP48	SPECIALTY CONSUMER CIRCUIT, PQFP48	SPECIALTY CONSUMER CIRCUIT, PQFP48
Number of functions	1	1	1
Number of terminals	48	48	48
Maximum operating temperature	70 Cel	70 Cel	70 Cel
Minimum operating temperature	0.0 Cel	0.0 Cel	0.0 Cel
Maximum supply/operating voltage	5.25 V	5.25 V	5.25 V
Minimum supply/operating voltage	4.75 V	4.75 V	4.75 V
Processing package description	9 X 9 MM, 1.40 MM HEIGHT, LEAD FREE, MS-022, TQFP-48	9 X 9 MM, 1.40 MM HEIGHT, LEAD FREE, MS-022, TQFP-48	9 X 9 MM, 1.40 MM HEIGHT, LEAD FREE, MS-022, TQFP-48
Lead-free	Yes	Yes	Yes
EU RoHS regulations	Yes	Yes	Yes
state	ACTIVE	ACTIVE	ACTIVE
packaging shape	SQUARE	SQUARE	SQUARE
Package Size	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
surface mount	Yes	Yes	Yes
Terminal form	GULL WING	GULL WING	GULL WING
Terminal spacing	0.5000 mm	0.5000 mm	0.5000 mm
terminal coating	MATTE TIN	MATTE TIN	MATTE TIN
Terminal location	QUAD	QUAD	QUAD
Packaging Materials	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL
Consumer IC Type	CONSUMER CIRCUIT	CONSUMER CIRCUIT	CONSUMER CIRCUIT

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