INTEGRATED CIRCUITS
74ALS651/74ALS651–1
74ALS652/74ALS652–1
Transceiver/register
Product specification
IC05 Data Handbook
1991 Feb 08
Philips
Semiconductors
Philips Semiconductors
Product specification
Transceiver/register
74ALS651/651-1
74ALS652/652-1
FEATURES
74ALS651/74ALS651-1
74ALS652/74ALS652-1
Octal transceiver/register, inverting (3-State)
Octal transceiver/register, non-inverting (3-State)
TYPE
74ALS651/74ALS651-1
74ALS652/74ALS652-1
TYPICAL
f
MAX
140MHz
140MHz
TYPICAL
SUPPLY CURRENT
(TOTAL)
40mA
46mA
•
Independent registers for A and B buses
•
Multiplexed real-time and stored data
•
Choice of non-inverting and inverting data paths
•
3-State outputs
•
The -1 versions sinks 48mA I
OL
within the
±5%
V
CC
range
DESCRIPTION
The 74LAS651 and 74ALS652 transceivers/registers consist of bus
transceiver circuits with 3-State outputs, D-type flip-flops, and
control circuitry arranged for multiplexed transmission of data
directly from the input bus or the internal registers. Data on the A or
B bus will be clocked into the registers as the appropriate clock pin
goes High. Output enable (OEAB, OEBA) and select (SAB, SBA)
pins are provided for bus management. The 74LAS651-1 and
74ALS652-1 will sink 48mA if the V
CC
is limited to 5.0V
±
0.25V.
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
74ALS651N, 74ALS651-1N,
74ALS652N, 74ALS652-1N
74ALS651D, 74ALS651-1D,
74ALS652D, 74ALS652-1D
DRAWING
NUMBER
24-pin plastic DIP
24-pin plastic SOL
SOT222-1
SOT137-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
A0 – A7
B0 – B7
CPAB
CPBA
SAB
SBA
OEAB
OEBA
A0 – A7, B0 – B7
A0 – A7, B0 – B7
A inputs
B inputs
A-to-B clock input
B-to-A clock input
A-to-B select input
B-to-A select input
A-to-B output enable input
B-to-A output enable input
A, B outputs
A, B outputs (-1 version)
DESCRIPTION
74ALS (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
750/240
750/480
LOAD VALUE
HIGH/LOW
70µA/0.1mA
70µA/0.1mA
20µA/0.1mA
20µA/0.1mA
20µA/0.1mA
20µA/0.1mA
20µA/0.1mA
20µA/0.1mA
15mA/24mA
15mA/48mA
NOTE:
One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
1991 Feb 08
2
853–1407 01670
Philips Semiconductors
Product specification
Transceiver/register
74ALS651/74ALS651-1
74ALS652/74ALS652-1
PIN CONFIGURATION – 74ALS651/651-1
CPAB
SAB
OEAB
A0
A1
A2
A3
A4
A5
1
2
3
4
5
6
7
8
9
24 V
CC
23 CPBA
22 SBA
21 OEBA
20 B0
19 B1
18 B2
17 B3
16 B4
15 B5
14 B6
13 B7
PIN CONFIGURATION – 74ALS652/652-1
CPAB
SAB
OEAB
A0
A1
A2
A3
A4
A5
1
2
3
4
5
6
7
8
9
24 V
CC
23 CPBA
22 SBA
21 OEBA
20 B0
19 B1
18 B2
17 B3
16 B4
15 B5
14 B6
13 B7
A6 10
A7 11
GND 12
A6 10
A7 11
GND 12
SC00127
SC00128
LOGIC SYMBOL – 74ALS651/651-1
4
5
6
7
8
9
10
11
LOGIC SYMBOL – 74ALS652/652-1
4
5
6
7
8
9
10
11
A0 A1 A2 A3 A4 A5 A6 A7
1
2
3
23
22
21
CPAB
SAB
OEAB
CPBA
SBA
OEBA
B0 B1 B2 B3 B4 B5 B6 B7
1
2
3
23
22
21
A0 A1 A2 A3 A4 A5 A6 A7
CPAB
SAB
OEAB
CPBA
SBA
OEBA
B0 B1 B2 B3 B4 B5 B6 B7
V
CC
= Pin 24
GND = Pin 12
20
19
18
17
16
15
14
13
SC00129
V
CC
= Pin 24
GND = Pin 12
20
19
18
17
16
15
14
13
SC00130
IEC/IEEE SYMBOL – 74ALS651/651-1
21
3
23
22
1
2
EN1 [AB]
G3
G5
C6
G7
1
1
6D
5
6
7
8
9
10
11
1
7
7
5
5
1
1
2
19
18
17
16
15
14
13
4D
20
EN1 [BA]
IEC/IEEE SYMBOL – 74ALS652/652-1
21
3
23
22
1
2
EN1 [AB]
G3
G5
C6
G7
1
1
6D
5
6
7
8
9
10
11
1
7
7
5
5
1
1
2
19
18
17
16
15
14
13
4D
20
EN1 [BA]
4
4
SC00131
SC00132
1991 Feb 08
3
Philips Semiconductors
Product specification
Transceiver/register
74ALS651/74ALS651-1
74ALS652/74ALS652-1
BUS MANAGEMENT FUNCTIONS
The following examples demonstrate the four fundamental
bus-management functions that can be performed with the
74ALS651/74ALS651-1 and 74ALS652/74ALS652-1. The select
pins determine whether data is stored or transferred through the
device in real time. The output enable pins determine the direction of
the data flow.
STORAGE FROM
A, B, OR A AND B
REAL TIME BUS TRANSFER
BUS B TO BUS A
REAL TIME BUS TRANSFER
BUS A TO BUS B
TRANSFER STORED DATA
TO A AND/OR B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
OEABOEBA CPAB CPBA SAB SBA
L
L
X
X
X
L
OEABOEBA CPAB CPBA SAB SBA
H
H
X
X
L
X
OEABOEBA CPAB CPBA SAB SBA
X
L
L
X
X
X
↑
X
↑
X
↑
↑
X
X
X
X
X
X
OEABOEBA CPAB CPBA SAB SBA
H
L
H or L H or L
H
H
SC00133
1991 Feb 08
4
Philips Semiconductors
Product specification
Transceiver/register
74ALS651/74ALS651-1
74ALS652/74ALS652-1
LOGIC DIAGRAM – 74ALS651/651-1
OEBA
OEAB
CPBA
SBA
SPAB
SAB
21
3
23
22
1
2
LOGIC DIAGRAM – 74ALS652/652-1
OEBA
OEAB
CPBA
SBA
SPAB
SAB
21
3
23
22
1
2
1 OF 8 CHANNELS
1D
C1
1 OF 8 CHANNELS
1D
C1
4
A0
1D
C1
20
B0
4
A0
1D
C1
20
B0
V
CC
= Pin 24
GND = Pin 12
TO 7 OTHER CHANNELS
SC00134
V
CC
= Pin 24
GND = Pin 12
TO 7 OTHER CHANNELS
SC00135
FUNCTION TABLE
INPUTS
OEAB
L
L
X
H
L
L
L
L
H
H
H
H
OEBA
H
H
H
H
X
L
L
L
H
H
L
L
CPAB
H or L
↑
↑
↑
H or L
↑
X
X
X
H or L
H or L
H or L
CPBA
H or L
↑
H or L
↑
↑
↑
X
H or L
X
X
H or L
H or L
SAB
X
X
X
L
X
X
X
X
L
H
H
H
SBA
X
X
X
X
S
L
L
H
X
X
H
H
An
Input
Input
Input
Input
Unspecified*
Output
Output
Output
Input
Input
Output
Output
DATA I/O
Bn
Input
Input
Unspecified*
Output
Input
Input
Input
Input
Output
Output
Output
Output
OPERATING MODE
74ALS651/74ALS651-1
Isolation
Store A and B data
Store A, hold B
Store A in both registers
Hold A, store B
Store B in both registers
Real time B data to A bus
Stored B data to A bus
Real time A data to B bus
Stored A data to B bus
Stored A data to B bus
Stored B data to A bus
74ALS652/74ALS652-1
Isolation
Store A and B data
Store A, hold B
Store A in both registers
Hold A, store B
Store B in both registers
Real time B data to A bus
Stored B data to A bus
Real time A data to B bus
Stored A data to B bus
Stored A data to B bus
Stored B data to A bus
NOTES:
H = High voltage level
L = Low voltage level
X = Don’t care
* = The data output function may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always
enabled, i.e., data at the bus pins will be stored on every Low-to-High transition of the clock.
↑
= Low-to-High clock transition
1991 Feb 08
5
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