512MB, 1GB: (x72, SR) 244-Pin DDR2 Registered MiniDIMM
Features
DDR2 SDRAM Registered MiniDIMM
MT9HTF6472(P)K – 512MB
MT9HTF12872(P)K – 1GB
For component specifications, refer to Micron’s Web site:
www.micron.com/products/dram/ddr2
Features
• 244-pin, mini dual in-line memory module
(MiniDIMM)
• Fast data transfer rates: PC2-3200, PC2-4200, or
PC2-5300
• Supports ECC error detection and correction
• 512MB (64 Meg x 72), 1GB (128 Meg x 72)
• V
DD
= V
DD
Q = +1.8V
• V
DDSPD
= +1.7V to +3.6V
• JEDEC standard 1.8V I/O (SSTL_18 compatible)
• Differential data strobe (DQS, DQS#) option
• Four-bit prefetch architecture
• DLL to align DQ and DQS transitions with CK
• Multiple internal device banks for concurrent
operation
• Supports duplicate output strobe (RDQS/RDQS#)
• Programmable CAS# latency (CL)
• Posted CAS# additive latency (AL)
• WRITE latency = READ latency - 1
t
CK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts
• Single rank
Figure 1:
244-Pin DIMM (MO-244 R/C “A”)
PCB Height: 30 mm (1.18 in)
Options
• Parity
• Package
244-pin DIMM (lead-free)
• Frequency/CAS latency
1
2.5ns @ CL = 5 (DDR2-800)
2.5ns @ CL = 6 (DDR2-800)
3ns @ CL = 5 (DDR2-667)
3.75ns @ CL = 4 (DDR2-533)
5.0ns @ CL = 3 (DDR2-400)
2
• PCB height
30mm (1.18in)
Marking
P
Y
-80E
-800
-667
-53E
-40E
Notes: 1. CL = CAS (READ) latency; registered mode
will add one clock cycle to CL.
2. Not recommended for future designs.
Table 1:
Address Table
512MB
1GB
8K
16K A[13:0]
8 BA[2:0]
1Gb (128Meg x 8)
1K A[9:0]
1 (S0#)
Refresh count
Row addressing
Device bank addressing
Device configuration
Column addressing
Module rank addressing
8K
16K A[13:0]
4 BA[1:0]
512Mb (64 Meg x 8)
1K A[9:0]
1 (S0#)
PDF: 09005aef817ab1fc/Source: 09005aef817ab1dd
HTF9C64_128x72K.fm - Rev. D 7/08 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
512MB, 1GB: (x72, SR) 244-Pin DDR2 Registered MiniDIMM
Features
Table 2:
Speed
Grade
-80E
-800
-667
-53E
-40E
Key Timing Parameters
Industry
Nomenclature
PC2-6400
PC2-6400
PC2-5300
PC2-4200
PC2-3200
Data Rate (MT/s)
CL = 6
–
800
–
–
–
CL = 5
800
667
667
–
–
CL = 4
533
533
533
533
400
CL = 3
–
–
400
400
400
t
RCD
(ns)
RP
(ns)
12.5
15
15
15
15
t
RC
(ns)
55
55
55
55
55
t
12.5
15
15
15
15
Table 3:
Part Numbers and Timing Parameters – 512MB
Base device: MT47H64M8
1
, 512Mb DDR2 SDRAM
Part Number
2
MT9HTF6472(P)KY-80E__
MT9HTF6472(P)KY-800__
MT9HTF6472(P)KY-667__
MT9HTF6472(P)KY-53E__
MT9HTF6472(P)KY-40E__
Module
Density
512MB
512MB
512MB
512MB
512MB
Configuration
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
Module
Bandwidth
6.4 GB/s
6.4 GB/s
5.3 GB/s
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
2.5ns/800 MT/s
2.5ns/800 MT/s
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
Latency
(CL -
t
RCD -
t
RP)
5-5-5
6-6-6
5-5-5
4-4-4
3-3-3
Table 4:
Part Numbers and Timing Parameters – 1GB
Base device: MT47H128M8
1
, 1Gb DDR2 SDRAM
Module
Density
1GB
1GB
1GB
1GB
1GB
Module
Bandwidth
6.4 GB/s
6.4 GB/s
5.3 GB/s
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
2.5ns/800 MT/s
2.5ns/800 MT/s
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
Latency
(CL -
t
RCD -
t
RP)
5-5-5
6-6-6
5-5-5
4-4-4
3-3-3
Part Number
2
MT9HTF12872(P)KY-80E__
MT9HTF12872(P)KY-800__
MT9HTF12872(P)KY-667__
MT9HTF12872(P)KY-53E__
MT9HTF12872(P)KY-40E__
Notes:
Configuration
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
1. The data sheets for the base devices can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and
PCB revisions. Consult factory for current revision codes. Example: MT9HTF12872KY-667A2.
PDF: 09005aef817ab1fc/Source: 09005aef817ab1dd
HTF9C64_128x72K.fm - Rev. D 7/08 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
512MB, 1GB: (x72, SR) 244-Pin DDR2 Registered MiniDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 5:
Pin Assignments
244-Pin MiniDIMM Front
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
Vss
RESET#
NC
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
V
SS
DQ18
DQ19
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
V
SS
DQ24
DQ25
V
SS
DQS3#
DQS3
V
SS
DQ26
DQ27
V
SS
CB0
CB1
V
SS
DQS8#
DQS8
V
SS
CB2
CB3
V
SS
NC
V
DD
Q
CKE0
V
DD
NC/BA2
E
RR
_O
UT
V
DD
Q
A11
A7
V
DD
A5
A4
Notes:
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
V
DD
Q
A2
V
DD
V
SS
V
SS
P
AR
_I
N
V
DD
A10/AP
BA0
V
DD
WE#
V
DD
Q
CAS#
V
DD
Q
NC
NC
V
DD
Q
NC
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
V
SS
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
DQS5#
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
SA2
NC
Vss
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7#
DQS7
V
SS
DQ58
DQ59
V
SS
SA0
SA1
Pin
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
Symbol
V
SS
DQ4
DQ5
V
SS
DM0/
RDQS0
NC/
RDQS#0
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1/
RDQS1
NC/
RDQS#1
V
SS
RFU
RFU
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2/
RDQS2
NC/
RDQS#2
V
SS
DQ22
DQ23
V
SS
244-Pin MiniDIMM Back
Pin
154
155
156
157
Symbol
DQ28
Pin
185
186
187
188
189
190
191
192
193
194
195
196
Symbol
A3
A1
V
DD
CK0
CK0#
V
DD
A0
BA1
V
DD
RAS#
V
DD
Q
S0#
V
DD
Q
ODT0
A13
V
DD
NC
V
SS
DQ36
DQ37
V
SS
Pin
216
Symbol
NC/
RDQS#5
217
V
SS
218 DQ46
219 DQ47
220
221
222
223
224
225
226
227
V
SS
DQ52
DQ29
V
SS
DM3/
RDQS3
158
NC/
RDQS#3
159
V
SS
DQ30
DQ31
V
SS
CB4
CB5
V
SS
160
161
162
163
164
165
166
DM8/ 197
RDQS8
167
NC/
198
RDQS#8
168
V
SS
199
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
CB6
CB7
V
SS
NC
V
DD
Q
NC
V
DD
NC
NC
V
DD
Q
A12
A9
V
DD
A8
A6
V
DD
Q
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
DQ53
V
SS
RFU
RFU
V
SS
DM6/
RDQS6
228
NC/
RDQS#6
229
V
SS
DQ54
230
231
232
233
234
235
236
DM4/
RDQS4
NC/
RDQS#4
V
SS
239
DQ38 240
DQ39 241
V
SS
DQ44
DQ45
V
SS
DM5/
RDQS5
DQ55
V
SS
DQ60
DQ61
V
SS
DM7/
RDQS7
237
NC/
RDQS#7
238
V
SS
DQ62
DQ63
V
SS
SDA
SCL
V
DDSPD
242
243
244
1. Pin 55 is NC for 512MB, or BA2 for 1GB.
PDF: 09005aef817ab1fc/Source: 09005aef817ab1dd
HTF9C64_128x72K.fm - Rev. D 7/08 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
512MB, 1GB: (x72, SR) 244-Pin DDR2 Registered MiniDIMM
Pin Assignments and Descriptions
Table 6:
Symbol
A[15:0]
Pin Descriptions
Type
Input
Description
Address inputs:
Provide the row address for ACTIVE commands, and the column address
and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA[2/1:0]) or all device banks (A10 HIGH). The address inputs also provide the
op-code during a LOAD MODE command. A[13:0] (512MB, 1GB). A[15:14] are connected for
parity.
Bank address inputs:
BA[2/1:0] define the device bank to which an ACTIVE, READ, WRITE,
or PRECHARGE command is being applied. BA[2/1:0] define which mode register (MR,
EMR1, EMR2, and EMR3) is loaded during the LOAD MODE command. BA[1:0] (512MB) and
BA[2:0] (1GB).
Clock:
CK and CK# are differential clock inputs. All control, command, and address input
signals are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data (DQ, DQS, and DQS#) is referenced to the crossings of CK and CK#.
Clock enable:
CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DDR2 SDRAM.
Input data mask:
DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with the input data, during a write access. DM is sampled on
both edges of DQS. Although the DM pins are input-only, DM loading is designed to match
that of the DQ and DQS pins. If RDQS is disabled, RDQS[8:0] become DM[8:0] and
RDQS#[8:0] are not used.
On-die termination:
ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR2 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input will
be ignored if disabled via the LOAD MODE command.
Parity input:
Parity bit for the address, RAS#, CAS#, and WE#.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Reset:
Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal
can be used during power-up to ensure that CKE is LOW and DQ are High-Z.
Chip select:
S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs:
These pins are used to configure the SPD EEPROM address range on
the I
2
C bus.
Serial clock for SPD EEPROM:
SCL is used to synchronize communication to and from the
SPD EEPROM.
Check bits.
Data input/output:
Bidirectional data bus.
Data strobe:
DQS# is only used when differential data strobe mode is enabled via the
LOAD MODE command. Output with read data. Edge-aligned with read data. Input with
write data. Center-aligned with write data.
Serial data:
SDA is a bidirectional pin used to transfer addresses and data into and out of
the SPD EEPROM on the module on the I
2
C bus.
Parity error output:
Parity error found on the command and address bus.
BA[2:0]
Input
CK0, CK0#
Input
CKE0
DM[8:0]
RDQS[8:0]
Input
Input
ODT0
Input
P
AR
_I
N
RAS#, CAS#, WE#
RESET#
S0#
SA[2:0]
SCL
CB[7:0]
DQ[63:0]
DQS[8:0],
DQS#[8:0]
SDA
E
RR
_O
UT
Input
Input
Input
Input
Input
Input
I/O
I/O
I/O
I/O
Output
(open
drain)
Output
(open
drain)
Supply
EVENT#
Temperature event:
The EVENT# pin is asserted by the temperature sensor when critical
temperature thresholds have been exceeded.
Power supply:
1.8V ±0.1V. The component V
DD
and V
DD
Q are connected to the module
V
DD
.
V
DD
/V
DD
Q
PDF: 09005aef817ab1fc/Source: 09005aef817ab1dd
HTF9C64_128x72K.fm - Rev. D 7/08 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
512MB, 1GB: (x72, SR) 244-Pin DDR2 Registered MiniDIMM
Pin Assignments and Descriptions
Table 6:
Symbol
V
DDSPD
V
REF
V
SS
NC
RFU
Pin Descriptions (Continued)
Type
Supply
Supply
Supply
–
–
Description
SPD EEPROM power supply:
+1.7V to +3.6V.
Reference voltage:
V
DD
/2.
Ground.
No connect:
These pins are not connected on the module.
Reserved for future use.
PDF: 09005aef817ab1fc/Source: 09005aef817ab1dd
HTF9C64_128x72K.fm - Rev. D 7/08 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
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