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MSM832WMB-35

Description
Standard SRAM, 32KX8, 35ns, CMOS, CQCC32, CERAMIC, LCC-32
Categorystorage    storage   
File Size455KB,10 Pages
ManufacturerAPTA Group Inc
Download Datasheet Parametric View All

MSM832WMB-35 Overview

Standard SRAM, 32KX8, 35ns, CMOS, CQCC32, CERAMIC, LCC-32

MSM832WMB-35 Parametric

Parameter NameAttribute value
MakerAPTA Group Inc
Parts packaging codeQFJ
package instructionQCCN, LCC32,.45X.55
Contacts32
Reach Compliance Codeunknown
ECCN code3A001.A.2.C
Maximum access time35 ns
I/O typeCOMMON
JESD-30 codeR-CQCC-N32
length14.03 mm
memory density262144 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count32768 words
character code32000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize32KX8
Output characteristics3-STATE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeQCCN
Encapsulate equivalent codeLCC32,.45X.55
Package shapeRECTANGULAR
Package formCHIP CARRIER
Parallel/SerialPARALLEL
power supply5 V
Certification statusNot Qualified
Filter levelMIL-STD-883
Maximum seat height2.03 mm
Maximum standby current0.04 A
Minimum standby current4.5 V
Maximum slew rate0.165 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal formNO LEAD
Terminal pitch1.27 mm
Terminal locationQUAD
width11.5 mm
MSM832 - 020/025/35
ISSUE 5.1 September 2002
32K x 8 SRAM
MSM832 - 025/35
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear
NE29 8SE, England Tel. +44 (0)191 2930500 Fax. +44 (0) 191 2590997
Issue 5.1 : September 2002
Description
The MSM832 is a high speed Static RAM organ-
ised as 32K x 8 available with access times of 25
or 35 ns. The device is available in ceramic 32
pad LCC package. It features completely static
operation with a low power standby mode and is
3.0V battery back-up compatible. It is directly TTL
compatible and has common data inputs and
outputs.
The device may be screened in accordance with
MIL-STD-883.
32,768 x 8 CMOS High Speed Static RAM
Features
• Fast Access Times of 25/35 ns.
• JEDEC Standard footprint.
• Operating Power
908 mW (max)
• Low Power Standby 11 mW (max) -L version.
• Low Voltage Data Retention.
• Directly TTL compatible.
• Completely Static Operation.
Block Diagram
Pin Definitions
A3
A4
A5
A6
A7
A8
A12
A13
A14
X
Address
Buffer
Row
Decoder
Memory Array
1 NC
32 Vcc
31 WE
30 A13
29
28
27
26
25
24
23
22
21
512 X 512
A7
A12
A14
4
3
2
D0
D7
I/O
Buffer
Column I/O
Column Decoder
WE
OE
Y Address Buffer
A6
A5
A4
A3
A2
A1
A0
NC
D0
5
6
7
8
9
10
11
12
13
14 D1
J,W
PACKAGE
TOP VIEW
A8
A9
A11
NC
OE
A10
CS
D7
D6
20 D5
19 D4
18 D3
17 NC
16 GND
15 D2
A0
A1
A2
A9
A10
A11
CS
Package Details
Pin Count
32
Description
Package Type
W
Leadless Chip Carrier (LCC)
Pin Functions
A0-A14
Address inputs
D0-7
Data Input/Output
CS
Chip Select
OE
Output Enable
WE
Write Enable
V
CC
Power(+5V)
GND
Ground

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