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IDT7134LA35CI

Description
Dual-Port SRAM, 4KX8, 35ns, CMOS, CDIP48, SIDE BRAZED, CERAMIC, DIP-48
Categorystorage    storage   
File Size109KB,11 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT7134LA35CI Overview

Dual-Port SRAM, 4KX8, 35ns, CMOS, CDIP48, SIDE BRAZED, CERAMIC, DIP-48

IDT7134LA35CI Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeDIP
package instructionSIDE BRAZED, CERAMIC, DIP-48
Contacts48
Reach Compliance Codenot_compliant
ECCN codeEAR99
Maximum access time35 ns
I/O typeCOMMON
JESD-30 codeR-CDIP-T48
JESD-609 codee0
length60.96 mm
memory density32768 bit
Memory IC TypeDUAL-PORT SRAM
memory width8
Number of functions1
Number of ports2
Number of terminals48
word count4096 words
character code4000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize4KX8
Output characteristics3-STATE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Encapsulate equivalent codeDIP48,.6
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply5 V
Certification statusNot Qualified
Maximum seat height4.826 mm
Maximum standby current0.004 A
Minimum standby current2 V
Maximum slew rate0.25 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperature20
width15.24 mm
HIGH-SPEED
4K x 8 DUAL-PORT
STATIC SRAM
IDT7134SA/LA
Features
High-speed access
– Military: 25/35/45/55/70ns (max.)
– Industrial: 25/35/55ns (max.)
– Commercial: 20/25/35/45/55/70ns (max.)
Low-power operation
– IDT7134SA
Active: 700mW (typ.)
Standby: 5mW (typ.)
– IDT7134LA
Active: 700mW (typ.)
Standby: 1mW (typ.)
Fully asynchronous operation from either port
Battery backup operation—2V data retention (LA only)
TTL-compatible; single 5V (±10%) power supply
Available in 48-pin DIP, LCC, Flatpack and 52-pin PLCC
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available for
selected speeds
Functional Block Diagram
R/W
L
CE
L
R/W
R
CE
R
OE
L
I/O
CONTROL
I/O
CONTROL
OE
R
I/O
0L
- I/O
7L
I/O
0R
- I/O
7R
A
0L
- A
11L
ADDRESS
DECODER
MEMORY
ARRAY
ADDRESS
DECODER
A
0R
- A
11R
2720 drw 01
JANUARY 2001
1
©2000 Integrated Device Technology, Inc.
DSC-2720/12
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