The MIC5800/5801 latched drivers are high-voltage, high-
current integrated circuits comprised of four or eight CMOS
data latches, a bipolar Darlington transistor driver for each
latch, and CMOS control circuitry for the common CLEAR,
STROBE, and OUTPUT ENABLE functions.
The bipolar/MOS combination provides an extremely low-
power latch with maximum interface flexibility. MIC5800
contains four latched drivers; MIC5801 contains eight latched
drivers.
Data input rates are greatly improved in these devices. With
a 5V supply, they will typically operate at better than 5MHz.
With a 12V supply, significantly higher speeds are
obtained.The CMOS inputs are compatible with standard
CMOS, PMOS, and NMOS circuits. TTL or DTL circuits may
require the use of appropriate pull-up resistors. The bipolar
outputs are suitable for use with relays, solenoids, stepping
motors, LED or incandescent displays, and other high-power
loads.Both units have open-collector outputs and integral
diodes for inductive load transient suppression. The output
transistors are capable of sinking 500mA and will sustain at
least 50V in the OFF state. Because of limitations on package
power dissipation, the simultaneous operation of all drivers at
maximum rated current can only be accomplished by a
reduction in duty cycle. Outputs may be paralleled for higher
load current capability.
Features
•
•
•
•
•
•
4.4MHz Minimum Data Input Rate
High-Voltage, Current Sink Outputs
Output Transient Protection
CMOS, PMOS, NMOS, and TTL Compatible Inputs
Internal Pull-Down Resistors
Low-Power CMOS Latches
Ordering Information
Part Number
Standard
MIC5800BN
MIC5800BM
MIC5801BN
5962-8764001WA
1
MIC5801BV
MIC5801BWM
1
Standard
Pb-Free
MIC5800YN
MIC5800YM
MIC5801YN
MIC5801YV
MIC5801YWM
Temperature Range
– 40°C to + 85°C
– 40°C to + 85°C
– 40°C to +85°C
– 55°C to +125°C
– 40°C to + 85°C
– 40°C to +85°C
Package
14–Pin Plastic DIP
14–Pin SOIC
22–Pin Plastic DIP
22–Pin CERDIP
28–Pin PLCC
24–Pin SOIC
Military Drawing number for MIC5801AJBQ
Functional Diagram
VDD
INn
COMMON
OUTn
STROBE
GND
CLEAR
OUTPUT
ENABLE
COMMON MOS
CONTROL
TYPICAL MOS
LATCH
TYPICAL BIPOLAR
DRIVER
Micrel, Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
March 2005
1
MIC5800/5801
MIC5800/5801
Micrel, Inc.
Typical Input
Absolute Maximum Ratings:
(Notes 1–6)
at +25°C Free-Air Temperature
Output Voltage, V
CE
Supply Voltage, V
DD
Input Voltage Range, V
IN
Continuous Collector Current, I
C
Package Power Dissipation:
MIC5800 Plastic DIP (Note 1)
MIC5801 Plastic DIP (Note 2)
MIC5800 SOIC (Note 3)
MIC5801 PLCC (Note 4)
MIC5801 CERDIP (Note 5)
MIC5801 Wide SOIC (Note 6)
Operating Temperature Range, T
A
Storage Temperature Range, T
S
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
V DD
50V
15V
–0.3V to V
DD
+ 0.3V
500mA
2.1W
2.5W
1.0W
2.25W
3.1W
1.4 Watt
–40°C to +85°C
–65°C to +125°C
IN
Derate at 16.7 mW/°C above T
A
= +25°C
Derate at 20 mW/°C above T
A
= +25°C
Derate at 8.5 mW/°C above T
A
= +25°C
Derate at 18.2 mW/°C above T
A
= +25°C
Derate at 25 mW/°C above T
A
= +25°C
Derate at 11 mW/°C above T
A
= +25°C
Micrel CMOS devices have input-static protection but are
susceptible to damage when exposed to extremely high static
electrical charges.
Pin Configuration
CLEAR
STROBE
IN1
IN2
IN3
IN4
GND
1
2
LATCHES
3
4
5
6
7
14 OE
13 VDD
12 OUT1
11 OUT2
10 OUT3
9 OUT4
8 COM
OE
CLEAR
STROBE
IN1
IN2
1
2
3
4
5
6
7
8
9
24 VDD
23 NC
22 OUT1
21 OUT2
20 OUT3
19 OUT4
18 OUT5
17 OUT6
16 OUT7
15 OUT8
14 NC
13 COM
MIC5800BN, BM
IN3
IN4
IN5
CLEAR
STROBE
IN1
IN2
IN3
IN4
IN5
IN6
IN7
1
2
3
4
LATCHES
5
6
7
8
9
22 OE
21 VDD
20 OUT1
19 OUT2
18 OUT3
17 OUT4
16 OUT5
15 OUT6
14 OUT7
13 OUT8
12 COM
IN6
IN7 10
IN8 11
GND 12
MIC5801BWM
IN8 10
GND 11
MIC5801BN, AJBQ
MIC5800/5801
2
March 2005
MIC5800/5801
Micrel, Inc.
Pin Configurations (continued)
STROBE
CLEAR
VDD
OE
NC
NC
NC
4
3
2
1
28 27 26
IN1 5
IN2 6
LATCHES
25 OUT1
24 OUT2
23 OUT3
22 OUT4
21 OUT5
20 OUT6
19 OUT7
IN3 7
IN4 8
IN5 9
IN6 10
IN7 11
12 13 14 15 16 17 18
IN8
NC
NC
COM
OUT8
NC
GND
MIC5801BV
Allowable Output Current As A Function of Duty Cycle
MIC5800BN, BM
ALLOWABLE COLLECTOR CURRENT IN mA AT 50°C
MIC5801BN, AJBQ
ALLOWABLE COLLECTOR CURRENT IN mA AT 50°C
450
400
350
300
250
200
150
100
0
10
20
30
40
50
60
70
80
90
100
NUMBER OF OUTPUTS
CONDUCTING
SIMULTANEOUSLY
4
2
3
1
450
400
350
300
250
200
150
100
0
NUMBER OF OUTPUTS
CONDUCTING
SIMULTANEOUSLY
10
20
30
40
50
60
70
80
90
100
6
7
8
4
5
3
1 or 2
PERCENT DUTY CYCLE
PERCENT DUTY CYCLE
March 2005
3
MIC5800/5801
MIC5800/5801
Micrel, Inc.
Electrical Characteristics
(Note 1)
:
at T
A
= +25°C, V
DD
= 5V (unless otherwise noted)
Limits
Characteristic
Output Leakage Current
Collector-Emitter
Saturation Voltage
Input Voltage
V
IN(0)
V
IN(1)
V
DD
= 12 V
V
DD
= 10 V
V
DD
= 5.0 V (See Note)
Input Resistance
R
IN
V
DD
= 12 V
V
DD
= 10 V
V
DD
= 5.0 V
Supply Current
I
DD(ON)
(Each
Stage)
I
DD(OFF)
(Total)
Clamp Diode
Leakage Current
Clamp Diode Forward Voltage
NOTE :
NOTE 1:
Symbol
I
CEX
V
CE(SAT)
Test Conditions
V
CE
= 50 V, T
A
= +25°C
V
CE
= 50 V, T
A
= +70°C
I
C
= 100 mA
I
C
= 200 mA
I
C
= 350 mA, V
DD
= 7.0 V
Min.
Typ.
Max. Units
50
100
µA
V
0.9
1.1
1.3
10.5
8.5
3.5
50
50
50
200
300
600
1.0
0.9
0.7
50
1.1
1.3
1.6
1.0
V
kΩ
V
DD
= 12 V, Outputs Open
V
DD
= 10 V, Outputs Open
V
DD
= 5.0 V, Outputs Open
V
DD
= 12 V, Outputs Open, Inputs = 0 V
V
DD
= 5.0 V, Outputs Open, Inputs = 0 V
V
R
= 50 V, T
A
= +25°C
V
R
= 50 V, T
A
= +70°C
I
F
= 350 mA
2.0
1.7
1.0
200
100
50
100
mA
µA
µA
V
I
R
V
F
1.7
2.0
Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to insure a minimum logic “1”.
Specification for packaged product only.
CLEAR
F
STROBE
OUTPUT
ENABLE
A
C
B
C
B
A
C
B
G
INN
D
OUT N
E
E
G
Timing Conditions
(Logic Levels are V
DD
and Ground)
A. Minimum data active time before strobe enabled (data set-up time) ....................................................................... 50ns
B. Minimum data active time after strobe disabled (data hold time) ............................................................................. 50ns
C. Minimum strobe pulse width ................................................................................................................................... 125ns
D. Typical time between strobe activation and output on to off transition ................................................................... 500ns
E. Typical time between strobe activation and output off to on transition ................................................................... 500ns
F. Minimum clear pulse width ..................................................................................................................................... 300ns
G. Minimum data pulse width ...................................................................................................................................... 225ns
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