AT89S52-24SJ datasheet, PDF - EEWORLD Datasheet

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AT89S52-24SJ: DescriptionMicrocontroller, 8-Bit, FLASH, 24MHz, CMOS, PDIP42, 0.600 INCH, PLASTIC, MS-011AC, DIP-42; CategoryThe embedded processor and controller Microcontrollers and processors; File Size479KB，39 Pages; ManufacturerAtmel (Microchip); Environmental Compliance

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AT89S52-24SJ Overview

Microcontroller, 8-Bit, FLASH, 24MHz, CMOS, PDIP42, 0.600 INCH, PLASTIC, MS-011AC, DIP-42

AT89S52-24SJ Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Atmel (Microchip)
Parts packaging code	DIP
package instruction	SDIP,
Contacts	42
Reach Compliance Code	compliant
core architecture	8051
Device core	8051
clock speed	24
Memory	0.25
flash memory	8
Has ADC	NO
Address bus width	16
bit size	8
maximum clock frequency	24 MHz
DAC channel	NO
DMA channel	NO
External data bus width	8
JESD-30 code	R-PDIP-T42
JESD-609 code	e3
length	36.83 mm
Humidity sensitivity level	1
Number of I/O lines	32
Number of terminals	42
On-chip program ROM width	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	NO
Package body material	PLASTIC/EPOXY
encapsulated code	SDIP
Package shape	RECTANGULAR
Package form	IN-LINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	245
Certification status	Not Qualified
RAM (bytes)	256
rom(word)	8192
ROM programmability	FLASH
Maximum seat height	4.83 mm
speed	24 MHz
Maximum supply voltage	5.5 V
Minimum supply voltage	4 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	THROUGH-HOLE
Terminal pitch	1.778 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
width	15.24 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

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Features

•

Compatible with MCS

-51 Products

•

8K Bytes of In-System Programmable (ISP) Flash Memory

•

– Endurance: 1000 Write/Erase Cycles

4.0V to 5.5V Operating Range

Fully Static Operation: 0 Hz to 33 MHz

Three-level Program Memory Lock

256 x 8-bit Internal RAM

32 Programmable I/O Lines

Three 16-bit Timer/Counters

Eight Interrupt Sources

Full Duplex UART Serial Channel

Low-power Idle and Power-down Modes

Interrupt Recovery from Power-down Mode

Watchdog Timer

Dual Data Pointer

Power-off Flag

Fast Programming Time

Flexible ISP Programming (Byte and Page Mode)

Green (Pb/Halide-free) Packaging Option

8-bit

Microcontroller

with 8K Bytes

In-System

Programmable

Flash

AT89S52

1. Description

The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K

bytes of in-system programmable Flash memory. The device is manufactured using

Atmel’s high-density nonvolatile memory technology and is compatible with the indus-

try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program

memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-

grammer. By combining a versatile 8-bit CPU with in-system programmable Flash on

a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a

highly-flexible and cost-effective solution to many embedded control applications.

The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes

of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a

six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,

and clock circuitry. In addition, the AT89S52 is designed with static logic for operation

down to zero frequency and supports two software selectable power saving modes.

The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and

interrupt system to continue functioning. The Power-down mode saves the RAM con-

tents but freezes the oscillator, disabling all other chip functions until the next interrupt

or hardware reset.

1919C–MICRO–3/05

4. Pin Description

4.1

VCC

Supply voltage.

4.2

GND

Ground.

4.3

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL

inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.

Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses

to external program and data memory. In this mode, P0 has internal pull-ups.

Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-

ing program verification.

External pull-ups are required during program verification.

4.4

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can

sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the inter-

nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low

will source current (I

) because of the internal pull-ups.

In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input

(P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the follow-

ing table.

Port 1 also receives the low-order address bytes during Flash programming and verification.

Port Pin

P1.0

P1.1

P1.5

P1.6

P1.7

Alternate Functions

T2 (external count input to Timer/Counter 2), clock-out

T2EX (Timer/Counter 2 capture/reload trigger and direction control)

MOSI (used for In-System Programming)

MISO (used for In-System Programming)

SCK (used for In-System Programming)

4.5

Port 2

Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can

sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the inter-

nal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low

will source current (I

) because of the internal pull-ups.

Port 2 emits the high-order address byte during fetches from external program memory and dur-

ing accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this

application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external

data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special

Function Register.

Port 2 also receives the high-order address bits and some control signals during Flash program-

ming and verification.

AT89S52

1919C–MICRO–3/05

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