K4C89183AF
Revision History
Version 0.0 (Oct. 2002)
- First Release
Version 0.01 (Nov. 2002)
- Changed die revision from D-die to F-die
- Corrected typo
- Corrected DQS to DS and QS(DQS -> DS and QS) in AC timing table and timing diagram.
Version 0.1 (Apr. 2003)
- Added 800Mbps(400Mhz) product
- Changed operating temperature from Ta to Tc.
- Changed capacitance of ADDR/CMD/CLK
From
Min
Addr/CMD/CLK
1.5
Max
2.5
Min
1.5
To
Max
3.0
Target
- Changed tDSS(DS input Falling Edge to Clock Setup Time)
From
F6
CL4
CL5
CL6
CL7
0.9
0.9
0.9
-
FB
0.9
0.9
0.9
-
F5
1.0
1.0
1.0
-
G7
0.75
0.75
0.75
0.75
F6
0.75
0.75
0.75
-
To
FB
0.8
0.8
0.8
-
F5
1.0
1.0
1.0
-
- Added CL7 for 800Mbps
- Deleted TSOP package outline
Version 0.11 (Apr. 2003)
- Corrected typo in page 3.(Deleted bi-directional strobe)
-
Corrected min. Vref to VDDQ/2x95% in page 7
Version 0.2 (Aug. 2003)
- Added package physical dimension
- Extracted 800Mbps(G7) binning from target spec ( G7 will be added in the future)
- Changed DC test condition
From
IDD1S,IDD2N,IDD2P,IDD5,IDD6
-
- Changed low frequency spec like below
From
Unit : ns
tCK max@CL=4
tCK max@CL=5
tCK max@CL=6
F6
7.5
7.5
7.5
FB
7.5
7.5
7.5
F5
7.5
7.5
7.5
F6
6.0
6.0
6.0
To
FB
6.0
6.0
6.0
F5
6.0
6.0
6.0
To
IDD1S,IDD2N,IDD2P,IDD5B,IDD6
IDD4W, IDD4R
Changed point
Changed condition
newly inserted
- Changed AC test load picture
- 2 -
REV. 0.2 Aug. 2003
K4C89183AF
4,194,304-WORDS x 4 BANKS x 18-BITS DOUBLE DATA RATE Network-DRAM
Target
DESCRIPTION
K4C89183AF is a CMOS Double Data Rate Network-DRAM containing 301,989,888 memory cells. K4C89183AF is organized as
4,194,304-words x 4 banks x18 bits. K4C89183AF feature a fully synchronous operation referenced to clock edge whereby all opera-
tions are synchronized at a clock input which enables high performance and simple user interface coexistence. K4C89183AF can oper-
ate fast core cycle compared with regular DDR SDRAM.
K4C89183AF is suitable for Server, Network and other applications where large memory density and low power consumption are
required. The Output Driver for Network-DRAM is capable of high quality fast data transfer under light loading condition.
FEATURES
Parameter
CL = 4
t
CK
Clock Cycle Time (min)
t
RC
Random Read/Write Cycle Time (min)
t
RAC
Random Access Time (min)
I
DD1S
Operating Current (single bank) (max)
I
DD2S
Power Down Current (max)
I
DD3S
Self-Refresh Current (max)
•
CL = 5
CL = 6
K4C89183AF
F6
4.0 ns
3.33 ns
3.0ns
20.0 ns
20.0 ns
TBD
TBD
TBD
FB
4.5 ns
3.75 ns
3.33 ns
22.5 ns
22.5 ns
TBD
TBD
TBD
F5
5.0 ns
4.5 ns
4.0 ns
25 ns
25 ns
TBD
TBD
TBD
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Fully Synchronous Operation
- Double Data Rate (DDR)
- Data input/output are synchronized with both edges of DS / QS.
- Differential Clock (CLK and CLK) inputs
- CS, FN and all address input signals are sampled on the positive edge of CLK.
- Output data (DQs and QS) is aligned to the crossings of CLK and CLK.
Fast clock cycle time of 3.0 ns minimum
- Clock : 333 MHz maximum
- Data : 666 Mbps/pin maximum
Quad Independent Banks operation
Fast cycle and Short Latency
Uni-directional Data Strobe
Distributed Auto-Refresh cycle in 3.9us
Self-Refresh
Power Down Mode
Variable Write Length Control
Write Latency = CAS Latency-1
Programable CAS Latency and Burst Length
- CAS Laatency = 4, 5, 6
- Burst Length = 2, 4
Organization : 4,194,304 words x 4 banks x 18 bits
Power Supply Voltage V
DD
: 2.5V
±
0.125V
V
DDQ
: 1.4V
∼
1.9V
1.8V CMOS I/O comply with SSTL - 1.8 (half strength driver) and HSTL
Package : 60Ball BGA, 1.0mm x 1.0mm Ball pitch
Notice : Network-DRAM is trademark of Samsung Electronics., Co LTD
- 3 -
REV. 0.2 Aug. 2003
Microcontroller MCU
京公网安备 11010802033920号
EEWORLD
