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NCP3418B
MOSFET Driver with Dual
Outputs for Synchronous
Buck Converters
The NCP3418B is a single Phase 12 V MOSFET gate driver
optimized to drive the gates of both high−side and low−side power
MOSFETs in a synchronous buck converter. The high−side and
low−side driver is capable of driving a 3000 pF load with a 25 ns
propagation delay and a 20 ns transition time.
With a wide operating voltage range, high or low side MOSFET
gate drive voltage can be optimized for the best efficiency. Internal
adaptive nonoverlap circuitry further reduces switching losses by
preventing simultaneous conduction of both MOSFETs.
The floating top driver design can accommodate VBST voltages as
high as 30 V, with transient voltages as high as 35 V. Both gate outputs
can be driven low by applying a low logic level to the Output Disable
(OD) pin. An Undervoltage Lockout function ensures that both driver
outputs are low when the supply voltage is low, and a Thermal
Shutdown function provides the IC with overtemperature protection.
The NCP3418B is pin−to−pin compatible with Analog Devices
ADP3418 with the following advantages:
Features
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MARKING
DIAGRAMS
8
8
1
SO−8
D SUFFIX
CASE 751
1
3418B
ALYW
G
DFN−10
MN SUFFIX
CASE 485C
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
3418B
ALYW
G
•
Faster Rise and Fall Times
•
Thermal Shutdown for System Protection
•
Internal Pulldown Resistor Suppresses Transient Turn On of Either
•
•
•
•
•
•
•
•
•
MOSFET
Anti Cross−Conduction Protection Circuitry
Floating Top Driver Accommodates Boost Voltages of up to 30 V
One Input Signal Controls Both the Upper and Lower Gate Outputs
Output Disable Control Turns Off Both MOSFETs
Complies with VRM10.x and VRM11.x Specifications
Undervoltage Lockout
Thermal Shutdown
Thermally Enhanced Package Available
These are Pb−Free Devices
PIN CONNECTIONS
BST
IN
OD
V
CC
1
BST
IN
OD
V
CC
V
CC
(Top View)
10
DRVH
SWN
PGND
PGND
DRVL
1
8
DRVH
SWN
PGND
DRVL
ORDERING INFORMATION
Device
NCP3418BDR2G
Package
SO−8
(Pb−Free)
Shipping
†
2500 Tape & Reel
3000 Tape & Reel
NCP3418BMNR2G DFN−10
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2006
1
March, 2006 − Rev. 5
Publication Order Number:
NCP3418B/D
NCP3418B
OD
3
V
CC
TSD
UVLO
IN
2
8
DRVH
1
BST
FALLING
EDGE
DELAY
FALLING
EDGE
DELAY
START
STOP
NON−OVERLAP
TIMERS
MONITOR
7
SWN
MONITOR
MIN DRVL
OFF TIMER
4
5
6
V
CC
DRVL
PGND
Figure 1. Block Diagram
PIN DESCRIPTION
SO−8
1
DFN−10
1
Symbol
BST
Description
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds
this bootstrap voltage for the high−side MOSFET as it is switched. The recommended capacitor value
is between 100 nF and 1.0
mF.
An external diode is required with the NCP3418B.
Logic−Level Input. This pin has primary control of the drive outputs.
Output Disable. When low, normal operation is disabled forcing DRVH and DRVL low.
Input Supply. A 1.0
mF
ceramic capacitor should be connected from this pin to PGND.
Input Supply. A 1.0
mF
ceramic capacitor should be connected from this pin to PGND.
Output drive for the lower MOSFET.
Power Ground. Should be closely connected to the source of the lower MOSFET.
Power Ground. Should be closely connected to the source of the lower MOSFET.
Switch Node. Connect to the source of the upper MOSFET.
Output drive for the upper MOSFET.
2
3
4
−
5
6
−
7
8
2
3
4
5
6
7
8
9
10
IN
OD
V
CC
V
CC
DRVL
PGND
PGND
SWN
DRVH
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2
NCP3418B
MAXIMUM RATINGS
Rating
Operating Ambient Temperature, T
A
Operating Junction Temperature, T
J
(Note 1)
Package Thermal Resistance: SO−8
Junction−to−Case, R
qJC
Junction−to−Ambient, R
qJA
(2−Layer Board)
Package Thermal Resistance: DFN−10 (Note 2)
Junction−to−Case, R
qJC
(From die to exposed pad)
Junction−to−Ambient, R
qJA
Storage Temperature Range, T
S
Lead Temperature Soldering (10 sec): Reflow (SMD styles only)
JEDEC Moisture Sensitivity Level
Pb−Free (Note 3)
SO−8 (260 peak profile)
Value
0 to 85
0 to 150
45
123
7.5
55
−65 to 150
260 peak
1
Unit
°C
°C
°C/W
°C/W
°C/W
°C/W
°C
°C
−
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Internally limited by thermal shutdown, 150°C min.
2. 2 layer board, 1 in
2
Cu, 1 oz thickness.
3. 60−180 seconds minimum above 237°C.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
MAXIMUM RATINGS
Pin Symbol
V
CC
BST
Pin Name
Main Supply Voltage Input
Bootstrap Supply Voltage Input
V
MAX
15 V
30 V wrt/PGND
35 V
v
50 ns wrt/PGND
15 V wrt/SW
30 V
BST + 0.3 V
35 V
v
50 ns wrt/PGND
15 V wrt/SW
V
CC
+ 0.3 V
V
CC
+ 0.3 V
V
CC
+ 0.3 V
0V
V
MIN
−0.3 V
−0.3 V wrt/SW
SW
DRVH
Switching Node
(Bootstrap Supply Return)
High−Side Driver Output
−1.0 V DC
−10 V< 200 ns
−0.3 V wrt/SW
DRVL
IN
OD
PGND
NOTE:
Low−Side Driver Output
DRVH and DRVL Control Input
Output Disable
Ground
−0.3 V DC
−2.0 V < 200 ns
−0.3 V
−0.3 V
0V
All voltages are with respect to PGND except where noted.
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3
NCP3418B
ELECTRICAL CHARACTERISTICS
(Note 4) (V
CC
= 12 V, T
A
= 0°C to +85°C, T
J
= 0°C to +125°C unless otherwise noted.)
Characteristic
Supply
Supply Voltage Range
Supply Current
OD Input
Input Voltage High
Input Voltage Low
Hysteresis
Input Current
Propagation Delay Time (Note 5)
PWM Input
Input Voltage High
Input Voltage Low
Hysteresis
Input Current
High−Side Driver
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Transition Times (Note 5)
Propagation Delay (Notes 5 & 6)
Low−Side Driver
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Timeout Delay
Transition Times
Propagation Delay
Undervoltage Lockout
UVLO Startup
UVLO Shutdown
Hysteresis
Thermal Shutdown
Over Temperature Protection
Hysteresis
4.
5.
6.
7.
−
(Note 7)
(Note 7)
150
−
170
20
−
−
°C
°C
−
−
−
−
−
−
3.7
3.2
0.3
3.9
3.5
0.4
4.4
3.9
0.7
V
V
V
−
−
−
t
rDRVL
t
fDRVL
t
pdhDRVL
t
pdlDRVL
V
CC
= 12 V (Note 7)
V
CC
− V
SW
= 12 V (Note 7)
DRVH−SW = 0
C
LOAD
= 3.0 nF
(See Figure 3)
(See Figure 3)
−
−
−
−
−
−
−
1.8
1.0
85
16
11
30
20
3.0
2.5
−
25
15
60
30
W
W
ns
ns
ns
ns
ns
−
−
t
rDRVH
t
fDRVH
t
pdhDRVH
t
pdlDRVH
V
BST
− V
SW
= 12 V (Note 7)
V
BST
− V
SW
= 12 V (Note 7)
V
BST
− V
SW
= 12 V, C
LOAD
= 3.0 nF
(See Figure 3)
V
BST
− V
SW
= 12 V
−
−
−
−
−
−
1.8
1.0
16
11
30
25
3.0
2.5
25
15
60
45
W
W
ns
ns
ns
ns
−
−
−
−
−
−
−
No internal pull−up or pull−down resistors
2.0
−
−
−1.0
−
−
500
−
−
0.8
−
+1.0
V
V
mV
mA
−
−
−
−
t
pdlOD
t
pdhOD
−
−
−
No internal pull−up or pull−down resistors
−
2.0
−
−
−1.0
30
30
−
−
500
−
50
50
−
0.8
−
+1.0
60
60
V
V
mV
mA
ns
ns
V
CC
I
SYS
−
BST = 12 V, IN = 0 V
4.6
−
−
2.0
13.2
6.0
V
mA
Symbol
Condition
Min
Typ
Max
Unit
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
AC specifications are guaranteed by characterization, but not production tested.
For propagation delays, “t
pdh
’’ refers to the specified signal going high; “t
pdl
’’ refers to it going low.
GBD: Guaranteed by design; not tested in production.
Specifications subject to change without notice.
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4
Embedded System
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