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21152-AB

Description
PCI Bus Controller, CMOS, PQFP160, PLASTIC, QFP-160
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size67KB,6 Pages
ManufacturerIntel
Websitehttp://www.intel.com/
Download Datasheet Parametric View All

21152-AB Overview

PCI Bus Controller, CMOS, PQFP160, PLASTIC, QFP-160

21152-AB Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Parts packaging codeQFP
package instructionQFP, QFP160,1.2SQ
Contacts160
Reach Compliance Codeunknow
ECCN code3A991.A.2
maximum clock frequency33 MHz
JESD-30 codeS-PQFP-G160
JESD-609 codee0
length28 mm
Number of terminals160
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeQFP
Encapsulate equivalent codeQFP160,1.2SQ
Package shapeSQUARE
Package formFLATPACK
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3.3,3.3/5 V
Certification statusNot Qualified
Maximum seat height3.75 mm
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width28 mm
uPs/uCs/peripheral integrated circuit typeBUS CONTROLLER, PCI
Base Number Matches1
PCI Bridges - Products: 21152 Transparent PCI-to-PCI Bridge
21152 Transparent PCI-to-PCI Bridge
The 21152AB transparent PCI-to-PCI Bridges is Not Recommended for new designs. For
33 MHz applications use the S21152BB.
The 21152 is designed for compliance with
PCI Local Bus Specification,
Revision 2.2. The
21152 is pin-to-pin compatible with the 21052 bridge, which is designed for compliance with
PCI Local Bus Specification,
Revision 2.0.
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The 21152 provides full support for delayed transactions, which enables the buffering of
memory read, I/O, and configuration transactions. The 21152 has separate posted write, read
data, and delayed transaction queues with significantly more buffering capability than
first-generation bridges. In addition, the 21152 supports buffering of simultaneous multiple
posted write and delayed transactions in both directions. Among the features provided by the
21152 are: a programmable 2-level secondary bus arbiter, individual secondary clock software
control, and enhanced address decoding. The 21152 has sufficient clock and arbitration pins to
support four PCI bus master devices directly on its secondary interface.
The 21152 allows the two PCI buses to operate concurrently. This means that a master and a
target on the same PCI bus can communicate while the other PCI bus is busy. This traffic
isolation may increase system performance in applications such as multimedia.
Features
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Designed for compliance with
PCI Local Bus Specification,
Revision 2.2
Implements delayed transactions for all PCI configuration, I/O, and memory read
commands up to three transactions simultaneously in each direction
Allows 88 bytes of buffering (data and address) for posted memory write commands in
each direction up to five posted write transactions simultaneously in each direction
Allows 72 bytes of read data buffering in each direction
Provides concurrent primary and secondary bus operation to isolate traffic
Provides five secondary clock outputs:
r
Low skew, permitting direct drive of option slots
r
Individual clock control through configuration space
Provides arbitration support for four secondary bus devices:
r
A programmable 2-level arbiter
r
Hardware disable control, permitting use of an external arbiter
Provides enhanced address decoding:
r
A 32-bit I/O address range
r
A 32-bit memory-mapped I/O address range
r
A 64-bit prefetchable memory address range
r
ISA-aware mode for legacy support in the first 64 KB of I/O address range
r
VGA addressing and VGA palette snooping support
Supports PCI transaction forwarding for the following commands:
r
All I/O and memory commands
r
Type 1 to Type 1 configuration commands
r
Type 1 to Type 0 configuration commands (downstream only)
r
All Type 1 to special cycle configuration command
Includes downstream lock support
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