M470L1624BT0
200pin DDR SDRAM SODIMM
128MB DDR SDRAM MODULE
(16Mx64 based on 16Mx16 DDR SDRAM)
200pin SODIMM
64-bit Non-ECC/Parity
Revision 0.2
Dec. 2001
Rev. 0.2 Dec. 2001
M470L1624BT0
Revision History
Revision 0.0 (Apr. 2001)
1. First release.
200pin DDR SDRAM SODIMM
Revision 0.1 (June. 2001)
1. Changed module current speificaton
2. Changed typo size on module PCB in package dimesions. (from 2.6mm to 3mm).
3. Changed AC parameter table.
Revision 0.2 (Dec. 2001)
- Add derating values for the specifications if the single-ended clock skew rate is less than 1.0V/ns in page 47.
- Revised "Absolute maximum rating" table in page 38.
. Changed "Voltage on VDDQ supply relative to VSS" value from -0.5~3.6V to -1~3.6V
. Changed "power dissipation" value from 1.0W to 1.5W.
- Revised AC parameter table
From
DDR266A
Min.
tHZ
tACmin
-400ps
tACmin
-400ps
0.25
10ns
Max.
tACmax
-400ps
tACmax
-400ps
DDR266B
Min.
tACmin
-400ps
tACmin
-400ps
0.25
10ns
Max.
tACmax
-400ps
tACmax
-400ps
DDR200
Min.
tACmin
-400ps
tACmin
-400ps
0.25
10ns
Max.
tACmax
-400ps
tACmax
-400ps
DDR266A
Min.
-0.75
Max.
+0.75
To
DDR266B
Min.
-0.75
Max.
+0.75
DDR200
Min.
-0.8
Max.
+0.8
tLZ
tWPST
(tCK)
tPDEX
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
0.4
7.5ns
0.6
0.4
7.5ns
0.6
0.4
10ns
0.6
-
Deleted typical current in IDD spec. table
-
Included address and control input setup/hold time(tIS/tIH) at slow slew rate in DDR200/266 AC specification
-
Deleted Exit self refresh to write command(tXSW) in DDR200/266 AC specification
-
Rename tXSA(exit self refresh to bank active command) to tXSNR(exit self refresh to non read command) at DDR200/266
-
Rename tXSR(exit self refresh to read command) to tXSRD at DDR200/266
-
Rename tWPREH(DQS in hold time) to tWPRE at DDR200/266
-
Rename tREF(Refresh interval time) to tREFI at DDR200/266
- Changed tWR value from 2tCK to 15ns.
--Rename tCDLR(Write data out to Read command) t0 tWTR
- Added tDAL(tWR+tRP)
Rev. 0.2 Dec. 2001
M470L1624BT0
200pin DDR SDRAM SODIMM
M470L1624BT0 200pin DDR SDRAM SODIMM
16Mx64 200pin DDR SDRAM SODIMM based on 16Mx16
GENERAL DESCRIPTION
The Samsung M470L1624BT0 is 16M bit x 64 Double Data
Rate SDRAM high density memory modules based on first gen
of 256Mb DDR SDRAM respectively.
The Samsung M470L1624BT0 consists of four CMOS16M x
16 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-
II(400mil) packages mounted on a 200pin glass-epoxy sub-
strate. Four 0.1uF decoupling capacitors are mounted on the
printed circuit board in parallel for each DDR SDRAM.
The M470L1624BT0 is Dual In-line Memory Modules and
intended for mounting into 200pin edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. Data I/O transactions are possible on both
edges of DQS. Range of operating frequencies, programmable
latencies and burst lengths allow the same device to be useful
for a variety of high bandwidth, high performance memory sys-
tem applications.
FEATURE
• Performance range
Part No.
Max Freq.
Interface
M470L1624BT0-C(L)A2 133MHz(7.5ns@CL=2)
M470L1624BT0-C(L)B0 133MHz(7.5ns@CL=2.5)
M470L1624BT0-C(L)A0 100MHz(10ns@CL=2)
• Power supply : Vdd: 2.5V
±
0.2V, Vddq: 2.5V
±
0.2V
SSTL_2
•
Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK )
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB :
Height 1250 (mil),
double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
Front
VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
/CK0
VSS
Key
DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
Pin
Front
Pin
Front
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
Back
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
Key
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
Pin
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
Back
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU/(RESET)
VSS
VSS
VDD
VDD
CKE0
DU(BA2)
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
/RAS
/CAS
/S1
DU
VSS
DQ36
DQ37
VDD
DM4
Pin
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
Back
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
/CK1
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU
67
DQ27
135
DQ34
69
VDD
137
VSS
71
CB0
139
DQ35
73
CB1
141
DQ40
75
VSS
143
VDD
77
DQS8 145
DQ41
79
CB2
147
DQS5
81
VDD
149
VSS
83
CB3
151
DQ42
85
DU
153
DQ43
87
VSS
155
VDD
89
CK2
157
VDD
91
/CK2
159
VSS
93
VDD
161
VSS
95
CKE1
163
DQ48
97 DU(A13) 165
DQ49
99
A12
167
VDD
101
A9
169
DQS6
103
VSS
171
DQ50
105
A7
173
VSS
107
A5
175
DQ51
109
A3
177
DQ56
111
A1
179
VDD
113
VDD
181
DQ57
115 A10/AP 183
DQS7
117
BA0
185
VSS
119
/WE
187
DQ58
121
/S0
189
DQ59
123
DU
191
VDD
125
VSS
193
SDA
127
DQ32
195
SCL
129
DQ33
197 VDDSPD
131
VDD
199 VDDID
133
DQS4
PIN DESCRIPTION
Pin Name
A0 ~ A12
BA0 ~ BA1
DQ0 ~ DQ63
DQS0 ~ DQS7
CK0~ CK2,
CK0 ~ CK2
CKE0
CS0
RAS
CAS
WE
DM0 ~ DM7
VDD
VDDQ
VSS
VREF
VDDSPD
SDA
SCL
SA0 ~ 2
VDDID
NC
*
Function
Address input (Multiplexed)
Bank Select Address
Data input/output
Data Strobe input/output
Clock input
Clock enable input
Chip select input
Row address strobe
Column address strobe
Write enable
Data - in mask
Power supply (2.5V)
Power Supply for DQS(2.5V)
Ground
Power supply for reference
Serial EEPROM Power
Supply ( 2.3V to 3.6V)
Serial data I/O
Serial clock
Address in EEPROM
VDD identification flag
No connection
These pins are not used in this module.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.2 Dec. 2001
M470L1624BT0
FUNCTIONAL BLOCK DIAGRAM
200pin DDR SDRAM SODIMM
S0
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
S
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
S
D0
D2
DQS1
DM1
DQS5
DM5
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
S
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ58
DQ60
DQ61
DQ62
DQ63
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
S
D1
D3
DQS3
DM3
DQS7
DM7
*Clock Net Wiring
Dram1
BA0 - BA1
A0 - A13
RAS
CAS
CKE0
WE
BA0-BA1: DDR SDRAMs D0 - D3
A0-A13: DDR SDRAMs D0 - D3
RAS : SDRAMs D0 - D3
CAS : SDRAMs D0 - D3
CKE: SDRAMs D0 - D3
WE: SDRAMs D0 - D3
Clock
Input
CK0/C K0
CK1/C K1
CK2/C K2
Clock Wiring
SDRAMs
2 SDRAMs
2 SDRAMs
NC
CK
CK
Card
Edge
R=120
Ω
±
5%
Cap
Dram3
Cap
V
DDSPD
V
D D
/V
DDQ
SPD
D0 - D3
D0 - D3
Serial PD
SCL
WP
A0
SA0
A1
SA1
A2
SA2
SDA
VREF
V
SS
V
DDID
D0 - D3
D0 - D3
Strap: see Note 4
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must
be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD
≠
VDDQ.
Rev. 0.2 Dec. 2001
M470L1624BT0
Absolute Maximum Rate
Parameter
Voltage on any pin relative to V
SS
Voltage on V
DD
& V
DDQ
supply relative to V
SS
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
200pin DDR SDRAM SODIMM
Value
-0.5 ~ 3.6
-1.0 ~ 3.6
-55 ~ +150
6
50
Unit
V
V
°C
W
mA
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to V
SS
=0V, T
A
=0 to 70°C)
Parameter
Supply voltage(for device with a nominal V
DD
of 2.5V)
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage(system)
Input logic high voltage
Input logic low voltage
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
Input crossing point voltage, CK and CK inputs
Input leakage current
Output leakage current
Output High Current(Normal strengh driver)
;V
OUT
= V
T T
+ 0.84V
Output High Current(Normal strengh driver)
;V
OUT
= V
T T
- 0.84V
Output High Current(Half strengh driver)
;V
OUT
= V
T T
+ 0.45V
Output High Current(Half strengh driver)
;V
OUT
= V
T T
- 0.45V
Symbol
V
DD
V
DDQ
V
REF
V
TT
V
I H
(DC)
V
IL
(DC)
V
I N
(DC)
V
I D
(DC)
V
IX
(DC)
I
I
I
O Z
I
OH
I
OL
I
OH
Min
2.3
2.3
VDDQ/2-50mV
V
REF
-0.04
V
REF
+0.15
-0.3
-0.3
0.3
1.15
-2
-5
-16.8
16.8
-9
Max
2.7
2.7
VDDQ/2+50mV
V
REF
+0.04
V
DDQ
+0.3
V
REF
-0.15
V
DDQ
+0.3
V
DDQ
+0.6
1.35
2
5
Unit
Note
V
V
V
V
V
V
V
V
uA
uA
mA
mA
mA
3
5
1
2
4
4
I
OL
9
mA
Notes
1. Includes
±
25mV margin for DC offset on V
REF
, and a combined total of
±
50mV margin for all AC noise and DC offset on V
REF
,
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V
REF
and internal DRAM noise coupled
TO V
REF
, both of which may result in V
REF
noise. V
REF
should be de-coupled with an inductance of
≤
3nH.
2.V
TT
is not applied directly to the device. V
T T
is a system supply for signal termination resistors, is expected to be set equal to
V
REF
, and must track variations in the DC level of V
REF
3. V
I D
is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the dc level of the same.
6. These charactericteristics obey the SSTL-2 class II standards.
Rev. 0.2 Dec. 2001