K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
1M x 16Bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 1,048,576 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory
cells within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (1K Ref. or 4K Ref.), access time (-50 or -60), power
consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-
before- RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This
1Mx16 Fast Page Mode DRAM family is fabricated using Samsung
′s
advanced CMOS process to realize high band-width, low power
consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machin es.
FEATURES
• Part Identification
-
-
-
-
K4F171611D-J(T) (5V, 4K Ref.)
K4F151611D-J(T) (5V, 1K Ref.)
K4F171612D-J(T) (3.3V, 4K Ref.)
K4F151612D-J(T) (3.3V, 1K Ref.)
• Fast Page Mode operation
• 2 CAS Byte/Word Read/Write operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
Unit : mW
• Available in 42-pin SOJ 400mil and 50(44)-pin TSOP(II)
400mil packages
• Single +5V±10% power supply (5V product)
• Single +3.3V
±0.3V
power supply (3.3V product)
5V
1K
504
468
4K
495
440
1K
770
715
•
Active Power Dissipation
3.3V
4K
-50
-60
324
288
Speed
•
Refresh Cycles
Part
NO.
K4F171611D
K4F171612D
K4F151611D
K4F151612D
V
CC
5V
3.3V
5V
3.3V
1K
16ms
Refresh
cycle
4K
Refresh period
Normal
64ms
128ms
L-ver
RAS
UCAS
LCAS
W
FUNCTIONAL BLOCK DIAGRAM
Control
Clocks
Vcc
Vss
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
Row Decoder
Sens e Amps & I/O
Lower
Data in
Buffer
Lower
Data out
Buffer
Upper
Data in
Buffer
Upper
Data out
Buffer
DQ0
to
DQ7
•
Perfomance Range
Speed
-50
-60
Memory Array
1,048,576 x16
Cells
OE
t
RAC
50ns
60ns
t
CAC
15ns
15ns
t
RC
90ns
110ns
t
PC
35ns
40ns
Remark
5V/3.3V
5V/3.3V
A0-A11
(A0 - A9)
*1
A0 - A7
(A0 - A9)
*1
Row Address Buffer
Col. Address Buffer
Column Decoder
DQ8
to
DQ15
Note)
*1
:
1K Refresh
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
PIN CONFIGURATION
(Top Views)
• K4F17(5)1611(2)D-J
• K4F17(5)1611(2)D-T
V
CC
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
N.C
N.C
W
RAS
*A11(N.C)
*A10(N.C)
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
V
SS
DQ15
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
N.C
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
V
SS
V
C C
DQ0
DQ1
DQ2
DQ3
V
C C
DQ4
DQ5
DQ6
DQ7
N.C
N.C
N.C
W
RAS
*A11(N.C)
*A10(N.C)
A0
A1
A2
A3
V
C C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
SS
DQ15
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
N.C
N.C
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
V
SS
*A10 and A11 are N.C for K4F151611(2)D(5V/3.3V,
1K Ref.
product)
J : 400mil 42 SOJ
T : 400mil 50(44) TSOP II
Pin Name
A0 - A11
A0 - A9
DQ0 - 15
V
SS
RAS
UCAS
LCAS
W
OE
V
C C
N.C
Pin Function
Address Inputs (4K Product)
Address Inputs (1K Product)
Data In/Out
Ground
Row Address Strobe
Upper Column Address Strobe
Lower Column Address Strobe
Read/Write Input
Data Output Enable
Power(+5V)
Power(+3.3V)
No Connection
K4F171611D, K4F151611D
K4F171612D, K4F151612D
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
3.3V
V
IN,
V
O U T
V
CC
Tstg
P
D
I
OS
Address
-0.5 to +4.6
-0.5 to +4.6
-55 to +150
1
50
Rating
5V
CMOS DRAM
Units
-1.0 to +7.0
-1.0 to +7.0
-55 to +150
1
50
V
V
°C
W
mA
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted
to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
Min
V
C C
V
SS
V
I H
V
IL
3.0
0
2.0
-0.3
*2
(Voltage referenced to Vss, T
A
= 0 to 70°C)
5V
Max
3.6
0
V
CC
+0.3
*1
0.8
Min
4.5
0
2.4
-1.0
*2
Typ
5.0
0
-
-
Max
5.5
0
V
CC
+1.0
*1
0.8
V
V
V
V
Units
3.3V
Typ
3.3
0
-
-
*1 : V
C C
+1.3V/15ns(3.3V), V
CC
+2.0V/20ns(5V), Pulse width is measured at V
C C
*2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at V
SS
DC AND OPERATING CHARACTERISTICS
Max
Parameter
(Recommended operating conditions unless otherwise noted.)
Symbol
I
I(L)
Min
-5
Max
5
Units
uA
Input Leakage Current (Any input 0≤V
IN
≤V
I N
+0.3V,
all other input pins not under test=0 Volt)
3.3V
Output Leakage Current
(Data out is disabled, 0V≤V
OUT
≤V
CC
)
Output High Voltage Level(I
O H
=-2mA)
Output Low Voltage Level(I
OL
=2mA)
Input Leakage Current (Any input 0≤V
IN
≤V
I N
+0.5V,
all other input pins not under test=0 Volt)
5V
Output Leakage Current
(Data out is disabled, 0V≤V
OUT
≤V
CC
)
Output High Voltage Level(I
O H
=-5mA)
Output Low Voltage Level(I
OL
=4.2mA)
I
O(L)
V
O H
V
OL
I
I(L)
-5
2.4
-
-5
5
-
0.4
5
uA
V
V
uA
I
O(L)
V
O H
V
OL
-5
2.4
-
5
-
0.4
uA
V
V
K4F171611D, K4F151611D
K4F171612D, K4F151612D
DC AND OPERATING CHARACTERISTICS
Symbol
Power
Speed
K4F171612D
I
C C 1
I
C C 2
I
C C 3
I
C C 4
I
C C 5
I
C C 6
I
C C 7
I
CCS
Don′t care
Normal
L
Don′t care
Don′t care
Normal
L
Don′t care
L
L
-50
-60
Don′t care
-50
-60
-50
-60
Don′t care
-50
-60
Don′t care
Don′t care
90
80
1
1
90
80
90
80
0.5
200
90
80
300
150
K4F151612D
140
130
1
1
140
130
90
80
0.5
200
140
130
200
150
CMOS DRAM
(Continued)
Max
K4F171611D
90
80
2
1
90
80
90
80
1
200
90
80
350
200
K4F151611D
140
130
2
1
140
130
90
80
1
200
140
130
250
200
mA
mA
mA
mA
mA
mA
mA
mA
mA
uA
mA
mA
uA
uA
Units
I
C C 1
* : Operating Current (RAS and UCAS, LCAS cycling @t
RC
=min.)
I
C C 2
: Standby Current (RAS=UCAS=LCAS=W=V
IH
)
I
C C 3
* : RAS-only Refresh Current (UCAS=LCAS=V
IH
, RAS cycling @t
R C
=min.)
I
C C 4
* : Fast Page Mode Current (RAS=V
IL
, UCAS or LCAS, Address cycling @t
PC
=min.)
I
C C 5
: Standby Current (RAS=UCAS=LCAS=W=V
CC
-0.2V)
I
C C 6
* : CAS-Before- RAS Refresh Current (RAS, UCAS or LCAS cycling @t
RC
=min.)
I
C C 7
: Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(V
IH
)=V
C C
-0.2V, Input low voltage(V
IL
)=0.2V, UCAS, LCAS=0.2V,
DQ=Don′t care, T
R C
=31.25us(4K/L-ver), 125us(1K/L-ver),
T
R A S
=T
RAS
min~300ns
I
C C S
: Self Refresh Current
RAS=UCAS =LCAS=V
IL
, W=OE=A0 ~ A11=V
C C
-0.2V or 0.2V,
DQ0 ~ DQ15=V
CC
-0.2V, 0.2V or Open
*Note :
I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
, I
C C 3
and I
CC6,
address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one fast page mode cycle time, t
PC
.
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CAPACITANCE
(T
A
=25
°C,
V
CC
=5V or 3.3V, f=1MHz)
Parameter
Input capacitance [A0 ~ A11]
Input capacitance [RAS, UCAS, LCAS, W, OE]
Output capacitance [DQ0 - DQ15]
Symbol
C
IN1
C
IN2
C
D Q
Min
-
-
-
CMOS DRAM
Max
5
7
7
Units
pF
pF
pF
AC CHARACTERISTICS
(0°C≤T
A
≤70°C,
See note 1,2)
Test condition (5V device) : V
C C
=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V
Test condition (3.3V device) : V
CC
=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
Parameter
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
Output buffer turn-off delay
Transition time (rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Symbol
Min
-50
Max
Min
110
155
50
15
25
0
0
3
30
50
13
50
13
20
15
5
0
10
0
10
25
0
0
0
10
10
13
13
10K
37
25
10K
13
50
0
0
3
40
60
15
60
15
20
15
5
0
10
0
10
30
0
0
0
10
10
15
15
10K
45
30
10K
15
50
60
15
30
-60
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
8
11
11
4
10
3,4,10
3,4,5
3,10
3
6
2
Units
Notes
t
R C
t
RWC
t
RAC
t
CAC
t
AA
t
CLZ
t
O F F
t
T
t
R P
t
RAS
t
RSH
t
CSH
t
CAS
t
RCD
t
RAD
t
CRP
t
ASR
t
RAH
t
ASC
t
CAH
t
RAL
t
RCS
t
RCH
t
RRH
t
WCH
t
W P
t
RWL
t
CWL
90
133
京公网安备 11010802033920号
EEWORLD
