4GB (x72, ECC, QR) 240-Pin 1.35V DDR3 Halogen-Free RDIMM
Features
1.35V DDR3 SDRAM Halogen-Free RDIMM
MT36KSZF51272PDZ – 4GB
Features
•
DDR3 functionality and operations supported as de-
fined in the component data sheet
•
240-pin, registered dual in-line memory module
(RDIMM)
•
Fast data transfer rates: PC3-10600, PC3-8500, or
PC3-6400
•
4GB (512 Meg x 72)
•
Vdd = 1.35V ±0.0675V
•
Backward-compatible with standard 1.5V DDR3 sys-
tems
•
Vddspd = +3.0V to +3.6V
•
Supports ECC error detection and correction
•
Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
•
Quad rank
•
On-board I
2
C temperature sensor with integrated
serial presence-detect (SPD) EEPROM
•
Fixed burst chop (BC) of 4 and burst length (BL) of 8
via the mode register set (MRS)
•
Selectable BC4 or BL8 on-the-fly (OTF)
•
Gold edge contacts
•
Halogen-free
•
Fly-by topology
•
Terminated control, command, and address bus
•
Full module heat spreader
Table 1: Key Timing Parameters
Speed
Grade
-1G4
-1G1
-1G0
-80C
-80B
Industry
Nomenclature
PC3-10600
PC3-8500
PC3-8500
PC3-6400
PC3-6400
Data Rate (MT/s)
CL = 10
1333
–
–
–
–
CL = 9
1333
–
–
–
–
CL = 8
1066
1066
1066
–
–
CL = 7
1066
1066
–
–
–
CL = 6
800
800
800
800
800
CL = 5
667
667
667
800
667
t
RCD
t
RP
t
RC
Figure 1: 240-Pin RDIMM (MO-269 R/C H)
PCB height: 30.0mm (1.181in)
U1
U2
U3
U4
U5
U6
U8
U9
U10
U11
U7
U12
U13
U14
U15
U16
U17
U18
U19
U20
Options
Operating temperature
–
Commercial (0°C
≤
T
A
≤
+70°C)
•
Package
–
240-pin DIMM (halogen-free)
•
Frequency/CAS latency
–
1.5ns @ CL = 9 (DDR3-1333)
–
1.87ns @ CL = 7 (DDR3-1066)
–
1.87ns @ CL = 8 (DDR3-1066)
1
–
2.5ns @ CL = 5 (DDR3-800)
1
–
2.5ns @ CL = 6 (DDR3-800)
1
Note:
Marking
None
Z
-1G4
-1G1
-1G0
-80C
-80B
1. Not recommended for new designs.
(ns)
13.125
13.125
15
12.5
15
(ns)
13.125
13.125
15
12.5
15
(ns)
49.125
50.625
52.5
50
52.5
PDF: 09005aef83a13f32
KSZF36C512x72PDZ.pdf - Rev. A 5/09
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2009
Micron Technology, Inc. All rights reserved.
4GB (x72, ECC, QR) 240-Pin 1.35V DDR3 Halogen-Free RDIMM
Features
Table 2: Addressing
Parameter
Refresh count
Row address
Device bank address
Device configuration
Column address
Module rank address
4GB
8K
16K A[13:0]
8 BA[2:0]
1Gb (128 Meg x 8)
1K A[9:0]
4 S#[3:0]
Table 3: Part Numbers and Timing Parameters – 4GB Modules
Base device: MT41J128M8,
1
1Gb DDR3 SDRAM
Module
2
Part Number
Density
Configuration
MT36KSZF51272PDZ-1G4__
MT36KSZF51272PDZ-1G1__
MT36KSZF51272PDZ-1G0__
MT36KSZF51272PDZ-80C__
MT36KSZF51272PDZ-80B__
Notes:
4GB
4GB
4GB
4GB
4GB
512 Meg x 72
512 Meg x 72
512 Meg x 72
512 Meg x 72
512 Meg x 72
Module
Bandwidth
10.6 GB/s
8.5 GB/s
8.5 GB/s
6.4 GB/s
6.4 GB/s
Memory Clock/
Data Rate
1.5ns/1333 MT/s
1.87ns/1066 MT/s
1.87ns/1066 MT/s
2.5ns/800 MT/s
2.5ns/800 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
9-9-9
7-7-7
8-8-8
5-5-5
6-6-6
1. The data sheet for the base device can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.
Consult factory for current revision codes. Example: MT36KSZF51272PDZ-1G1F1.
PDF: 09005aef83a13f32
KSZF36C512x72PDZ.pdf - Rev. A 5/09
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2009
Micron Technology, Inc. All rights reserved.
4GB (x72, ECC, QR) 240-Pin 1.35V DDR3 Halogen-Free RDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 4: Pin Assignments
240-Pin DDR3 RDIMM Front
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VrefDQ
Vss
DQ0
DQ1
Vss
DQS0#
DQS0
Vss
DQ2
DQ3
Vss
DQ8
DQ9
Vss
DQS1#
DQS1
Vss
DQ10
DQ11
Vss
DQ16
DQ17
Vss
DQS2#
DQS2
Vss
DQ18
DQ19
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
DQ25
Vss
DQS3#
DQS3
Vss
DQ26
DQ27
Vss
CB0
CB1
Vss
DQS8#
DQS8
Vss
CB2
CB3
Vss
Vtt
Vtt
CKE0
Vdd
BA2
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
A2
Vdd
NC
NC
Vdd
Vdd
VrefCA
Par_In
Vdd
A10
BA0
Vdd
WE#
CAS#
Vdd
S1#
ODT1
Vdd
S2#
Vss
DQ32
DQ33
Vss
DQS4#
DQS4
Vss
DQ34
DQ35
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
DQ41
Vss
DQS5#
DQS5
Vss
DQ42
DQ43
Vss
DQ48
DQ49
Vss
DQS6#
DQS6
Vss
DQ50
DQ51
Vss
DQ56
DQ57
Vss
DQS7#
DQS7
Vss
DQ58
DQ59
Vss
SA0
SCL
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
Vss
DQ4
DQ5
Vss
DM0/
TDQS9
240-Pin DDR3 RDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
151
152
153
154
155
Vss
181
A1
Vdd
Vdd
CK0
CK0#
Vdd
211
212
213
214
215
216
Vss
DM5/
TDQS14
NU/
TDQS14#
Vss
DQ46
DQ47
Vss
DQ52
DQ53
Vss
DM6/
TDQS15
NU/
TDQS15#
Vss
DQ54
DQ55
Vss
DQ60
DQ61
Vss
DM7/
TDQS16
DM7/
TDQS16#
Vss
DQ62
DQ63
Vss
SA1
SDA
DM3/ 182
TDQS12
NU/
183
TDQS12#
Vss
DQ30
DQ31
Vss
CB4
CB5
Vss
184
185
186
NU/
156
TDQS9#
Vss
DQ6
DQ7
Vss
DQ12
DQ13
Vss
DM0/
TDQS9
157
158
159
160
161
162
163
164
187 EVENT# 217
188
189
190
A0
Vdd
BA1
Vdd
RAS#
S0#
Vdd
ODT0
A13
Vdd
S3#
Vss
DQ36
DQ37
Vss
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
DM8/ 191
TDQS17
NU/
192
TDQS17#
Vss
CB6
CB7
Vss
NC
RESET#
CKE1
Vdd
A15
A14
Vdd
A12
A9
Vdd
A8
A6
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
NU/
165
TDQS9#
Vss
DQ14
DQ15
Vss
DQ20
DQ21
Vss
166
167
168
169
170
171
172
53 Err_Out# 83
54
55
56
57
58
Vdd
A11
A7
Vdd
A5
84
85
86
87
88
DM2/ 173
TDQS11
NU/
174
TDQS11#
Vss
DQ22
DQ23#
Vss
175
176
177
178
DM4/ 233
TDQS13
NU/
234
TDQS13#
Vss
DQ38
DQ39
Vss
235
237
238
236 Vddspd
PDF: 09005aef83a13f32
KSZF36C512x72PDZ.pdf - Rev. A 5/09
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2009
Micron Technology, Inc. All rights reserved.
4GB (x72, ECC, QR) 240-Pin 1.35V DDR3 Halogen-Free RDIMM
Pin Assignments and Descriptions
Table 4: Pin Assignments (Continued)
240-Pin DDR3 RDIMM Front
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
29
30
Vss
DQ24
59
60
A4
Vdd
89
90
Vss
DQ40
119
120
SA2
Vtt
149
150
DQ28
DQ29
240-Pin DDR3 RDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
179
180
Vdd
A3
209
210
DQ44
DQ45
239
240
Vss
Vtt
Table 5: Pin Descriptions
Symbol
A[15:0]
Type
Input
Description
Address inputs:
Provide the row address for ACTIVATE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out
of the memory array in the respective bank. A10 is sampled during a PRECHARGE com-
mand to determine whether the PRECHARGE applies to one bank (A10 LOW, bank selec-
ted by BA[2:0]) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is
selected by BA. A12 is also used for BC4/BL8 identification as “BL on-the-fly” during CAS
commands. The address inputs also provide the op-code during the mode register com-
mand set. A[13:0] address the 1Gb DDR3 devices. A[15:14] are needed to calculate parity
on the command/address bus.
Bank address inputs:
BA[2:0] define the device bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register
(MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command. BA[2:0] are used
as part of the parity calculation.
Clock:
CK and CK# are differential clock inputs. All control, command, and address input
signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#.
Clock enable:
CKE enables (registered HIGH) and disables (registered LOW) internal circui-
try and clocks on the DRAM.
Input data mask:
DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with the input data, during a write access. DM is sampled on
both edges of the DQS. Although the DM pins are input-only, the DM loading is designed
to match that of the DQ and DQS pins. When TDQS is enabled, DM is disabled and TDQS
and TDQS# provide termination resistance; otherwise, the TDQS# pins are no function.
On-die termination:
ODT enables (registered HIGH) and disables (registered LOW) termi-
nation resistance internal to the DRAM. When enabled in normal operation, ODT is only
applied to the following pins: DQ, DQS, DQS#, and DM. The ODT input will be ignored if
disabled via the LOAD MODE command.
Parity input:
Parity bit for the address, RAS#, CAS#, and WE#.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being en-
tered.
Reset:
RESET# is an active LOW CMOS input referenced to Vss. The RESET# input receiver is
a CMOS input defined as a rail-to-rail signal with DC HIGH
≥
0.8 × Vdd and DC LOW
≤
0.2 ×
Vdd. RESET# assertions and desertions are asynchronous.
Chip select:
S# enables (registered LOW) and disables (registered HIGH) the command de-
coder.
Serial address inputs:
These pins are used to configure the temperature sensor/SPD EE-
PROM address range on the I
2
C bus.
BA[2:0]
Input
CK0, CK0#
CKE[1:0]
DM[8:0]
(TDQS[17:9]
TDQS#[17:9])
Input
Input
Input
ODT[1:0]
Input
Par_In
RAS#, CAS#,
WE#
RESET#
Input
Input
Input
(LVCMOS)
Input
Input
S#[3:0]
SA[2:0]
PDF: 09005aef83a13f32
KSZF36C512x72PDZ.pdf - Rev. A 5/09
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2009
Micron Technology, Inc. All rights reserved.
4GB (x72, ECC, QR) 240-Pin 1.35V DDR3 Halogen-Free RDIMM
Pin Assignments and Descriptions
Table 5: Pin Descriptions (Continued)
Symbol
SCL
CB[7:0]
DQ[63:0]
DQS[8:0]
DQS#[8:0]
SDA
Err_Out#
EVENT#
Vdd
Vddspd
VrefCA
VrefDQ
Vss
Vtt
NC
NU
Type
Input
I/O
I/O
I/O
I/O
Description
Serial clock for temperature sensor/SPD EEPROM:
SCL is used to synchronize communi-
cation to and from the temperature sensor/SPD EEPROM.
Check bits:
Data used for ECC.
Data input/output:
Bidirectional data bus.
Data strobe:
DQS and DQS# are differential data strobes. Output with read data. Edge-
aligned with read data. Input with write data. Center-aligned with write data.
Serial data:
SDA is a bidirectional pin used to transfer addresses and data into and out of
the temperature sensor/SPD EEPROM on the module on the I
2
C bus.
Output
Parity error output:
Parity error found on the command and address bus.
(open drain)
Output
Temperature event:
The EVENT# pin is asserted by the temperature sensor when critical
(open drain) temperature thresholds have been exceeded.
Supply
Supply
Supply
Supply
Supply
Supply
–
–
Power supply:
1.5V ±0.075V. The component Vdd and Vddq are connected to the module
Vdd.
Temperature sensor/SPD EEPROM power supply:
+3.0V to +3.6V.
Reference voltage:
Control, command, and address (Vdd/2).
Reference voltage:
DQ, DM (Vdd/2).
Ground.
Termination voltage:
Used for control, command, and address (Vdd/2).
No connect:
These pins are not connected on the module.
Not used:
These pins are not used in specific module configuration/operations.
PDF: 09005aef83a13f32
KSZF36C512x72PDZ.pdf - Rev. A 5/09
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2009
Micron Technology, Inc. All rights reserved.
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