To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
7th.July.2000 Ver. 1.1
MITSUBISHI LSIs
M5M5V108DFP,VP,KV -70HI
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
DESCRIPTION
The M5M5V108DFP,VP,KV are a 1048576-bit CMOS static RAM
organized as 131072 word by 8-bit which are fabricated using high-
performance triple-polysilicon and double metal CMOS technology.
The use of thin film transistor (TFT) load cells and CMOS periphery
result in a high density and low power static RAM.
They are low standby current and low operation current and ideal
for the battery back-up application.
The M5M5V108DVP,KV are packaged in a 32-pin thin small
outline package which is a high reliability and high density surface
mount device(SMD).
PIN CONFIGURATION (TOP VIEW)
ADDRESS
INPUTS
FEATURES
Access
time
(max)
Power supply current
Type name
M5M5V108DFP,VP,KV-70HI
V
CC
Active stand-by
(1MHz)
(max)
(max)
70ns
2.7~3.6V
5mA
24µA
DATA
INPUTS/
OUTPUTS
NC
1
A
16 2
A
14 3
A
12 4
A
7 5
A
6 6
A
5 7
A
4 8
A
3 9
A
2 10
A
1 11
A
0 12
DQ
1 13
DQ
2 14
DQ
3 15
GND
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
ADDRESS
A
15
INPUT
S
2
CHIP SELECT
INPUT
W
WRITE CONTROL
INPUT
A
13
A
8
ADDRESS
INPUTS
A
9
A
11
OUTPUT ENABLE
OE
INPUT
A
10
ADDRESS
INPUT
S
1
CHIP SELECT
INPUT
DQ
8
DQ
7
DQ
6
DATA
INPUTS/
DQ
5
OUTPUTS
DQ
4
Directly TTL compatible : All inputs and outputs
Easy memory expansion and power down by S
1
,S
2
Data hold on +2V power supply
Three-state outputs : OR - tie capability
OE prevents data contention in the I/O bus
Common data I/O
Package
M5M5V108DFP
············
32pin 525mil SOP
2
M5M5V108DVP,RV
············
32pin 8 X 20 mm TSOP
2
M5M5V108DKV,KR
············
32pin 8 X 13.4 mm TSOP
A
11
A
9
A
8
A
13
W
S
2
A
15
V
CC
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
Outline 32P2M-A
OE
A
10
S
1
DQ
8
DQ
7
DQ
6
DQ
5
DQ
4
GND
DQ
3
DQ
2
DQ
1
A
0
A
1
A
2
A
3
APPLICATION
Small capacity memory units
M5M5V108DVP,KV
25
24
23
22
21
20
19
18
17
Outline 32P3H-E(VP), 32P3K-B(KV)
NC : NO CONNECTION
1
7th.July.2000 Ver. 1.1
MITSUBISHI LSIs
M5M5V108DFP,VP,KV -70HI
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5V108D series are determined by
a combination of the device control inputs S
1
,S
2
,W and OE.
Each mode is summarized in the function table.
A write cycle is executed whenever the low level W overlaps with
the low level S
1
and the high level S
2
. The address must be set up
before the write cycle and must be stable during the entire cycle.
The data is latched into a cell on the trailing edge of W,S
1
or
S
2
,whichever occurs first,requiring the set-up and hold time relative
to these edge to be maintained. The output enable input OE
directly controls the output stage. Setting the OE at a high level,
the output stage is in a high-impedance state, and the data bus
contention problem in the write cycle is eliminated.
A read cycle is executed by setting W at a high level and OE at a
low level while S
1
and S
2
are in an active state(S
1
=L,S
2
=H).
When setting S
1
at a high level or S
2
at a low level, the chip are in
a non-selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high- impedance
state, allowing OR-tie with other chips and memory expansion by
S
1
and S
2
. The power supply current is reduced as low as the
stand-by current which is specified as I
CC3
or I
CC4
, and the memory
data can be held at +2V power supply, enabling battery back-up
operation during power failure or power-down operation in the non-
selected mode.
FUNCTION TABLE
S
1
X
H
L
L
L
S
2
L
X
H
H
H
W
X
X
L
H
H
Mode
DQ
OE
X Non selection High-impedance
X Non selection High-impedance
Din
X
Write
Dout
L
Read
High-impedance
H
I
CC
Stand-by
Stand-by
Active
Active
Active
Note 1: "H" and "L" in this table mean VIH and VIL, respectively.
2: "X" in this table should be "H" or "L".
BLOCK DIAGRAM
*
A3 9
A2 10
A5 7
A6 6
A7
5
17
18
15
14
13
12
11
10
7
*
21
22
13 DQ1
14 DQ2
15 DQ3
17 DQ4
18 DQ5
19 DQ6
20 DQ7
21 DQ8
DATA
INPUTS/
OUTPUTS
A12 4
A14 3
A16 2
A15 31
131072 WORDS
X 8 BITS
( 512 ROWS
X128 COLUMNS
X 16BLOCKS )
23
25
26
27
28
29
ADDRESS
INPUTS
A13 28
A8 27
A9 26
A11 25
4
3
2
1
5
A4
8
16
19
20
31
32
8
24
30
6
WRITE
29 W CONTROL
INPUT
22 S1
30 S2
CHIP
SELECT
INPUTS
CLOCK
GENERATOR
A1 11
A0 12
A10 23
OUTPUT
24 OE ENABLE
INPUT
32 V
CC
16 GND
(0V)
* Pin numbers inside dotted line show those of TSOP
2
7th.July.2000 Ver. 1.1
MITSUBISHI LSIs
M5M5V108DFP,VP,KV -70HI
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
V
I
V
O
P
d
T
opr
T
stg
Supply voltage
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
With respect to GND
Ta=25°C
Parameter
Conditions
Ratings
– 0.3*~4.6
– 0.3*~Vcc + 0.3
(Max 4.6)
0~Vcc
700
– 40~85
– 65~150
Unit
V
V
V
mW
°C
°C
* –3.0V in case of AC ( Pulse width
≤
30ns )
DC ELECTRICAL CHARACTERISTICS
(Ta=– 40~85°C, Vcc=2.7~3.6V, unless otherwise noted)
Symbol
V
IH
V
IL
V
OH1
V
OH2
V
OL
I
I
I
O
I
CC1
I
CC2
Parameter
High-level input voltage
Low-level input voltage
High-level output voltage 1
High-level output voltage 2
Low-level output voltage
Input current
Output current in off-state
Active supply current
Active supply current
Test conditions
Limits
Min
2.0
I
OH
= – 0.5mA
I
OH
= – 0.05mA
I
OL
= 2mA
V
I
=0~Vcc
S
1
=V
IH
or S
2
=V
IL
or OE=V
IH
V
I/O
=0~V
CC
S
1
=V
IL
,S
2
=V
IH
,
other inputs=V
IH
or V
IL
Output-open(duty 100%)
1) S
2
≤
0.2V
other inputs=0~V
CC
2) S
1
≥
V
CC
–0.2V,
S
2
≥
V
CC
–0.2V
other inputs=0~V
CC
S
1
=V
IH
or S
2
=V
IL
,
other inputs=0~V
CC
70ns
100ns
1MHz
~25°C
~40°C
-HI
~70°C
~85°C
–0.3*
2.4
Vcc
– 0.5
0.4
±1
±1
35
30
5
1.2
3.6
12
24
0.33
mA
µA
mA
Typ
Max
Vcc
+ 0.3
0.6
Unit
V
V
V
V
V
µA
µA
I
CC3
Stand-by current
I
CC4
Stand-by current
* –3.0V in case of AC ( Pulse width
≤
30ns )
CAPACITANCE
(Ta=– 40~85°C, unless otherwise noted)
Symbol
C
I
C
O
Parameter
Input capacitance
Output capacitance
Test conditions
V
I
=GND, V
I
=25mVrms, f=1MHz
V
O
=GND,V
O
=25mVrms, f=1MHz
Min
Limits
Typ
Max
8
10
Unit
pF
pF
Note 3: Direction for current flowing into an IC is positive (no mark).
4: Typical value is Vcc = 3V, Ta = 25°C
3
7th.July.2000 Ver. 1.1
MITSUBISHI LSIs
M5M5V108DFP,VP,KV -70HI
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS
(Ta=– 40~85°C, unless otherwise noted )
(1) MEASUREMENT CONDITIONS
V
CC
................................. 2.7~3.6V
Input pulse level ............. V
IH
=2.2V,V
IL
=0.4V
Input rise and fall time ..... 5ns
Reference level ............... V
OH
=V
OL
=1.5V
Output loads ................... Fig.1, C
L
=30pF
C
L
=5pF (for t
en
,t
dis
)
Transition is measured ± 500mV from steady
state voltage. (for t
en
,t
dis
)
DQ
C
L
including
scope and JIG
1TTL
Fig.1 Output load
(2) READ CYCLE
Limits
Symbol
t
CR
t
a(A)
t
a(S1)
t
a(S2)
t
a(OE)
t
dis(S1)
t
dis(S2)
t
dis(OE)
t
en(S1)
t
en(S2)
t
en(OE)
t
V(A)
Parameter
Read cycle time
Address access time
Chip select 1 access time
Chip select 2 access time
Output enable access time
Output disable time after S
1
high
Output disable time after S
2
low
Output disable time after OE high
Output enable time after S
1
low
Output enable time after S
2
high
Output enable time after OE low
Data valid time after address
-70HI
Min
Max
70
70
70
70
35
25
25
25
10
10
5
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3) WRITE CYCLE
Symbol
t
CW
t
w(W)
t
su(A)
t
su(A-WH)
t
su(S1)
t
su(S2)
t
su(D)
t
h(D)
t
rec(W)
t
dis(W)
t
dis(OE)
t
en(W)
t
en(OE)
Parameter
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to W
Chip select 1 setup time
Chip select 2 setup time
Data setup time
Data hold time
Write recovery time
Output disable time from W low
Output disable time from OE high
Output enable time from W high
Output enable time from OE low
Limits
-70HI
Min
Max
70
55
0
65
65
65
30
0
0
25
25
5
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
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