M36LLR8760M1ZAQT datasheet, PDF

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M36LLR8760M1ZAQT: DescriptionMemory Circuit, 16MX16, CMOS, PBGA88, 8 X 10 MM, 0.80 MM PITCH, LFBGA-88; Categorystorage storage; File Size428KB，19 Pages; ManufacturerNumonyx ( Micron ); Websitehttps://www.micron.com

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M36LLR8760M1ZAQT Overview

Memory Circuit, 16MX16, CMOS, PBGA88, 8 X 10 MM, 0.80 MM PITCH, LFBGA-88

M36LLR8760M1ZAQT Parametric

Parameter Name	Attribute value
Maker	Numonyx ( Micron )
Parts packaging code	BGA
package instruction	LFBGA,
Contacts	88
Reach Compliance Code	unknown
Other features	PSEUDO SRAM IS ORGANIZED AS 4M X 16; SYNCHRONOUS BURST MODE OPERATION ALSO POSSIBLE
JESD-30 code	R-PBGA-B88
JESD-609 code	e0
length	10 mm
memory density	268435456 bit
Memory IC Type	MEMORY CIRCUIT
memory width	16
Number of functions	1
Number of terminals	88
word count	16777216 words
character code	16000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-25 °C
organize	16MX16
Package body material	PLASTIC/EPOXY
encapsulated code	LFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	8 mm

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M36LLR8760T1, M36LLR8760D1

M36LLR8760M1, M36LLR8760B1

256 + 128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory

64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package

TARGET SPECIFICATION

FEATURES SUMMARY

■

MULTI-CHIP PACKAGE

– 1 die of 256 Mbit (16Mb x16, Multiple

Bank, Multi-level, Burst) Flash Memory

– 1 die of 128 Mbit (8Mb x16, Multiple Bank,

Multi-Level, Burst) Flash Memory

– 1 die of 64 Mbit (4Mb x16) Pseudo SRAM

SUPPLY VOLTAGE

– V

DDF1

= V

DDF2

= V

CCP

= V

DDQF

= 1.7 to

1.95V

– V

PPF

= 9V for fast program (12V tolerant)

ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Top Configuration (Top + Top)

M36LLR8760T1: 880Dh + 88C4h

– Mixed Configuration (Bottom + Top)

M36LLR8760D1: 880Eh + 88C4h

– Mixed Configuration (Top + Bottom)

M36LLR8760M1: 880Dh + 88C5h

– Bottom Configuration (Bottom + Bottom)

M36LLR8760B1: 880Eh + 88C5h

PACKAGE

– Compliant with Lead-Free Soldering

Processes

– Lead-Free Versions

Figure 1. Package

FBGA

LFBGA88 (ZAQ)

8 x 10mm

■

FLASH MEMORIES

■

SYNCHRONOUS / ASYNCHRONOUS READ

– Synchronous Burst Read mode: 54MHz

– Asynchronous Page Read mode

– Random Access: 85ns

SYNCHRONOUS BURST READ SUSPEND

PROGRAMMING TIME

– 10µs typical Word program time using

Buffer Enhanced Factory Program

command

MEMORY ORGANIZATION

– Multiple Bank Memory Array:

16 Mbit Banks for the 256 Mbit Memory

8 Mbit Banks for the 128 Mbit Memory

– Parameter Blocks (at Top or Bottom)

COMMON FLASH INTERFACE (CFI)

100,000 PROGRAM/ERASE CYCLES per

BLOCK

DUAL OPERATIONS

– program/erase in one Bank while read in

others

– No delay between read and write

operations

SECURITY

– 64 bit unique device number

– 2112 bit user programmable OTP Cells

BLOCK LOCKING

– All blocks locked at power-up

– Any combination of blocks can be locked

with zero latency

– WP

for Block Lock-Down

– Absolute Write Protection with V

PPF

= V

PSRAM

■

ACCESS TIME: 70ns

ASYNCHRONOUS PAGE READ

– Page Size: 16 words

– Subsequent read within page: 20ns

LOW POWER FEATURES

– Temperature Compensated Refresh

(TCR)

– Partial Array Refresh (PAR)

– Deep Power-Down (DPD) Mode

SYNCHRONOUS BURST READ/WRITE

1/19

July 2005

This is preliminary information on a new product forseen to be developed. Details are subject to change without notice.

M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

FLASH MEMORIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. LFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Address Inputs (A0-A23). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Wait (WAIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Flash Chip Enable Inputs (E

, E

).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Flash Output Enable Inputs (G

, G

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Flash Write Enable (W

).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Flash Write Protect (WP

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Flash Reset (RP

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PSRAM Chip Enable input (E

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PSRAM Write Enable (W

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PSRAM Output Enable (G

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PSRAM Upper Byte Enable (UB

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PSRAM Lower Byte Enable (LB

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PSRAM Configuration Register Enable (CR

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

DDF1

DDF2

Supply Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

CCP

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

DDQF

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PPF

Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 2. Main Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 4. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2/19

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