RC82545GM datasheet, PDF - EEWORLD Datasheet

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RC82545GM: DescriptionLAN Controller, 1 Channel(s), 125MBps, CMOS, PBGA364, 21 X 21 MM, 1 MM PITCH, BGA-364; CategoryThe embedded processor and controller Microcontrollers and processors; File Size267KB，54 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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RC82545GM Overview

LAN Controller, 1 Channel(s), 125MBps, CMOS, PBGA364, 21 X 21 MM, 1 MM PITCH, BGA-364

RC82545GM Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	BGA
package instruction	LBGA, BGA364,20X20,40
Contacts	364
Reach Compliance Code	compli
Other features	ALSO REQUIRES 2.5V AND 3.3V SUPPLIES
Address bus width	64
boundary scan	YES
Bus compatibility	PCI
maximum clock frequency	25 MHz
Maximum data transfer rate	125 MBps
External data bus width	64
JESD-30 code	S-PBGA-B364
JESD-609 code	e0
length	21 mm
low power mode	YES
Number of serial I/Os	1
Number of terminals	364
Maximum operating temperature	55 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA364,20X20,40
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)	240
power supply	1.5,2.5,3.3 V
Certification status	Not Qualified
Maximum seat height	1.7 mm
Maximum supply voltage	1.57 V
Minimum supply voltage	1.43 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	21 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches	1

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82545GM Gigabit Ethernet Controller

Networking Silicon

Datasheet

Product Features

•

PCI/PCI-X

— PCI-X Revision 1.0a support for

frequencies up to 133 MHz

— Multi-function PCI device

— PCI Revision 2.3 support for 32-bit wide

or 64-bit wide interface at 33 MHz and

66 MHz

•

MAC

— IEEE 802.3x compliant flow control

support with software controllable pause

times and threshold values

— Programmable host memory receive

buffers (256 Bytes to 16 Kbytes) and

cache line size (16 Bytes to 256 Bytes)

— Wide, optimized internal data path

architecture (128 bits)

— 64 Kbyte configurable Transmit and

Receive FIFO buffers

— Optimized descriptor fetching and write-

back mechanisms

•

PHY

— Integrated PHY for 10/100/1000 Mbps

full and half duplex operation

— IEEE 802.3ab Auto-Negotiation support

— IEEE 802.3ab PHY compliance and

compatibility

— PHY ability to automatically detect

polarity and cable lengths and MDI

versus MDI-X cable at all speeds

Host Offloading

— Transmit and receive IP, TCP and UDP

checksum off-loading capabilities

— Transmit TCP segmentation

— IEEE 802.1q VLAN support with

VLAN tag insertion, stripping and

packet filtering for up to 4096 VLAN

tags

— Advanced packet filtering

Manageability

— Manageability features on both ports:

SMB port, ASF 1.0, ACPI, Wake on

LAN, and PXE

— Compliance with PCI Power

Management 1.1 and ACPI 2.0 register

set compliant

Four activity and link indication outputs that

directly drive LEDs

Lead-free

364-pin Ball Grid Array (BGA).

Devices that are lead-free are marked with

a circled “e1” and have the product code:

PCxxxxxx.

•

a. This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an impurity at <1000 ppm.

The Material Declaration Data Sheet, which includes lead impurity levels and the concentration of other Restriction on Haz-

ardous Substances (RoHS)-banned materials, is available at:

ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmarks

In addition, this device has been tested and conforms to the same parametric specifications as previous versions of the de-

vice. For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales representative.

322559-001

Revision 2.2

August 2009

Revision History

Revision

1.0

1.1

Date

Mar 2003

Nov 2003

Initial release.

Removed Confidential Status.

Modified power specification tables in Section 4.0.

Added a ball pad dimension drawing for the 82545GM device in Section 5.0.

1.2

Sept 2004

Corrected the nominal impedance values for the I/O cells from 50 kohms to a

nominal impedance value of 120 kohms, with a minimum of 90 kohms and a

maximum of 190 kohms.

Added Specification Change and Specification Clarification information from

the 82545GM Gigabit Ethernet Controller Specification Update.

Added a more detailed AUX_PWR pin description.

Added tristate and XOR non-JTAG test modes description.

Added lead free information.

Updated Table 3.

Updated section 5.2, table 3.

Description

1.5

June 2005

2.0

2.1

2.2

Sept 2005

Feb 2007

Aug 2009

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not

intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 82545GM may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current

characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-

548-4725 or by visiting Intel's website at http://www.intel.com.

Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.

*Third-party brands and names are the property of their respective owners.

Datasheet

Networking Silicon — 82545GM

Contents

1.0

Introduction......................................................................................................................... 1

1.1

1.2

1.3

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

3.0

3.1

3.2

Document Scope................................................................................................... 2

Reference Documents........................................................................................... 2

Product Code ........................................................................................................ 3

PCI ........................................................................................................................ 5

MAC Specific......................................................................................................... 5

PHY Specific ......................................................................................................... 5

Host Offloading...................................................................................................... 5

Manageability ........................................................................................................ 6

Additional Device................................................................................................... 6

Technology............................................................................................................ 7

Signal Type Definitions.......................................................................................... 9

PCI Bus Interface .................................................................................................. 9

3.2.1 PCI Address, Data and Control Signals ................................................. 10

3.2.2 Arbitration Signals .................................................................................. 11

3.2.3 Interrupt Signal ....................................................................................... 11

3.2.4 System Signals....................................................................................... 12

3.2.5 Error Reporting Signals .......................................................................... 12

3.2.6 Power Management Signals .................................................................. 12

3.2.7 Impedance Compensation Signals......................................................... 13

3.2.8 SMB Signals........................................................................................... 13

EEPROM Interface Signals ................................................................................. 13

Flash Interface Signals........................................................................................ 14

Miscellaneous Signals......................................................................................... 14

3.5.1 LED Signals............................................................................................ 14

3.5.2 Software Definable Signals .................................................................... 14

PHY Signals ........................................................................................................ 15

3.6.1 Crystal Signals ....................................................................................... 15

3.6.2 Analog Signals ....................................................................................... 15

Serializer / Deserializer (SERDES) Signals ........................................................ 16

JTAG Test Interface Signals ............................................................................... 16

Power Supply Connections ................................................................................. 16

3.9.1 Power Support Signals........................................................................... 16

3.9.2 Digital Supplies....................................................................................... 17

3.9.3 Analog Supplies ..................................................................................... 17

3.9.4 Ground and No Connects....................................................................... 17

XOR Testing........................................................................................................ 19

4.1.1 XOR Tree Control and Operation........................................................... 19

4.1.2 Pins Tested ............................................................................................ 20

Tristate Mode ...................................................................................................... 21

4.2.1 Tristate Mode Control and Operation ..................................................... 21

Additional 82545GM Features............................................................................................ 5

Signal Descriptions.............................................................................................................9

3.3

3.4

3.5

3.6

3.7

3.8

3.9

4.0

Test Port Functionality...................................................................................................... 19

4.1

4.2

Datasheet

iii

82545GM — Networking Silicon

4.2.2

5.0

5.1

5.2

5.3

5.4

5.5

5.6

Tristate Mode Using JTAG (TAP)........................................................... 21

Voltage, Temperature, and Timing Specifications ........................................................... 23

Targeted Absolute Maximum Ratings ................................................................. 23

Recommended Operating Conditions ................................................................. 23

DC Specifications ................................................................................................ 24

AC Characteristics .............................................................................................. 28

Serial Interface Specifications ............................................................................. 29

Timing Specifications .......................................................................................... 30

5.6.1 PCI/PCI-X Bus Interface ........................................................................ 30

5.6.2 Link Interface Timing .............................................................................. 33

5.6.3 Flash Interface ....................................................................................... 36

5.6.4 EEPROM Interface................................................................................. 37

Device Identification ........................................................................................... 39

Lead-Free Device Identification .......................................................................... 40

Package Information ........................................................................................... 41

Thermal Specifications........................................................................................ 43

Ball Mapping Diagram ......................................................................................... 44

Pinout Information ............................................................................................... 44

6.0

Package and Pinout Information ...................................................................................... 39

6.1

6.2

6.3

6.4

6.5

6.6

Datasheet

Networking Silicon — 82545GM

1.0

Introduction

The Intel

82545GM Gigabit Ethernet Controller is a single, compact component with an

integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) functions. The

Intel

82545GM enables Gigabit Ethernet implementations in a very small area and can be used

for desktop and workstation PC network designs as well as backplane applications with critical

space constraints.

The Intel

82545GM integrates Intel’s fourth generation gigabit MAC and PHY to provide a

standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T

applications (802.3, 802.3u, and 802.3ab). The controller is capable of transmitting and receiving

data at rates of 1000 Mbps, 100 Mbps, or 10 Mbps. In addition, it provides a 64-bit wide direct

Peripheral Component Interconnect (PCI) 2.3 and PCI-X 1.0a compliant interface capable of

operating at frequencies up to 133 MHz.

The Intel

82545GM on-board System Management Bus (SMB) port enables network

manageability implementations required by information technology personnel for remote control

and alerting through the LAN. Using the SMB, management packets can be routed to or from a

management processor. The SMB port enables industry standards, such as Intelligent Platform

Management Interface (IPMI) and Alert Standard Format (ASF), to be implemented using the

82545GM. In addition, on chip ASF 1.0 circuitry provides alerting and remote control capabilities

with standardized interfaces.

The 82545GM Gigabit Ethernet Controller architecture is designed to deliver high performance

and PCI/PCI-X bus efficiency. Wide internal data paths eliminate performance bottlenecks by

efficiently handling large address and data words. Combining a parallel and pipe-lined logic

architecture optimized for Gigabit Ethernet and independent transmit and receive queues, the

82545GM controller efficiently handles packets with minimum latency. The 82545GM controller

includes advanced interrupt handling features to limit PCI bus traffic and a PCI interface that

maximizes the use of bursts for efficient bus usage. The 82545GM is able to cache up to 64 packet

descriptors in a single burst for efficient PCI bandwidth use. A large 64-Kbyte on-chip packet

buffer maintains superior performance as available PCI bandwidth changes. By using hardware

acceleration, the controller is able to offload tasks, such as checksum calculations and TCP

segmentation, from the host processor.

Datasheet

RC82545GM Related Products

	RC82545GM	PC82545GM
Description	LAN Controller, 1 Channel(s), 125MBps, CMOS, PBGA364, 21 X 21 MM, 1 MM PITCH, BGA-364	LAN Controller, 1 Channel(s), 125MBps, CMOS, PBGA364, 21 X 21 MM, 1 MM PITCH, LEAD FREE, BGA-364
Is it lead-free?	Contains lead	Lead free
Is it Rohs certified?	incompatible	conform to
Parts packaging code	BGA	BGA
package instruction	LBGA, BGA364,20X20,40	LBGA, BGA364,20X20,40
Contacts	364	364
Reach Compliance Code	compli	compli
Other features	ALSO REQUIRES 2.5V AND 3.3V SUPPLIES	ALSO REQUIRES 2.5V AND 3.3V SUPPLIES
Address bus width	64	64
boundary scan	YES	YES
Bus compatibility	PCI	PCI
maximum clock frequency	25 MHz	25 MHz
Maximum data transfer rate	125 MBps	125 MBps
External data bus width	64	64
JESD-30 code	S-PBGA-B364	S-PBGA-B364
JESD-609 code	e0	e1
length	21 mm	21 mm
low power mode	YES	YES
Number of serial I/Os	1	1
Number of terminals	364	364
Maximum operating temperature	55 °C	55 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LBGA	LBGA
Encapsulate equivalent code	BGA364,20X20,40	BGA364,20X20,40
Package shape	SQUARE	SQUARE
Package form	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)	240	260
power supply	1.5,2.5,3.3 V	1.5,2.5,3.3 V
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.7 mm	1.7 mm
Maximum supply voltage	1.57 V	1.57 V
Minimum supply voltage	1.43 V	1.43 V
Nominal supply voltage	1.5 V	1.5 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	TIN LEAD	TIN SILVER COPPER
Terminal form	BALL	BALL
Terminal pitch	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	30	40
width	21 mm	21 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, LAN	SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches	1	1

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