EEWORLDEEWORLDEEWORLD

Part Number

Search

420-12.8M-5DD-TS-TR

Description
HCMOS/TTL Output Clock Oscillator, 12.8MHz Nom, ROHS COMPLIANT, J-LEADED, PLASTIC, SMD, 4 PIN
CategoryPassive components    oscillator   
File Size145KB,3 Pages
ManufacturerOscilent
Websitehttp://www.oscilent.com
Environmental Compliance
Download Datasheet Parametric View All

420-12.8M-5DD-TS-TR Overview

HCMOS/TTL Output Clock Oscillator, 12.8MHz Nom, ROHS COMPLIANT, J-LEADED, PLASTIC, SMD, 4 PIN

420-12.8M-5DD-TS-TR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Reach Compliance Codecompli
Other featuresTRI-STATE; ENABLE/DISABLE FUNCTION; TAPE AND REEL
maximum descent time8 ns
Frequency Adjustment - MechanicalNO
frequency stability100%
Manufacturer's serial number420
Installation featuresSURFACE MOUNT
Nominal operating frequency12.8 MHz
Maximum operating temperature70 °C
Minimum operating temperature-20 °C
Oscillator typeHCMOS/TTL
physical size14.0mm x 9.8mm x 4.7mm
longest rise time8 ns
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountYES
maximum symmetry60/40 %
Base Number Matches1
Oscilent Corporation | 420 Series Surface Mount Crystal Oscillator
Page 1 of 3
SMD Oscillators
Series Number
Package
Description
Last Modified
420
FEATURES
- Low Jitter
- Extended temperature range capabilities
- Tape and Reel
- Tri-State enable / disable
- 5V or 3.3V optional
- RoHs / Lead Free compliant
Plastic J-Lead
HCMOS / TTL Output
Jan. 01 2007
OPERATING CONDITIONS / ELECTRICAL CHARACTERISTICS
PARAMETERS
Output Logic
Input Voltage (VDD)
Frequency Range (f
O
)
Operating Temperature (T
OPR
)
Storage Temperature (T
STG
)
Frequency Stability
CONDITIONS
-
-
-
-
-
a+b+c+d
(a) Frequency Tolerance
(b) Temperature Stability
(c) Input Voltage Stability
(d) Load Stability
Input Current (I
DD
)
Aging
Rise Time (T
R
) / Fall Time (T
F
)
PIN 1 Tri-State
Output Voltage High "1" VOH
Output Voltage Low "0" VOL
Duty Cycle
Start-Up Time (T
S
)
Jitter (RMS)
-
@ 25°C
-
-
TTL Load
HCMOS Load
TTL Load
HCMOS Load
-
1~ 26 MHz
26 ~ 66.667 MHz
1.000 ~ 50.000 MHz
50.100 ~ 79.900 MHz
80.000 ~ 150.000 MHz
2.7 min.
0.4 max.
0.5 max.
50 ±10 (Std.) / 50 ±5 (Option)
4 max.
10 max.
±10 max.
±5 max.
±3 max.
CHARACTERISTICS
HCMOS / TTL Output
3.3 ±10%
1.0 ~ 150.000
0 ~ +70 Std. (Ext Temp Avail. See Table Below)
-55 ~ +125
±50, ±100 max. (Tighter Stability Avail.)
Inclusive of Overall Stability
Inclusive of Overall Stability (Operating Temperature)
Inclusive of Overall Stability (VDD ±10%)
Inclusive of Overall Stability (RL ±5%)
10 ~ 35 max.
±5 max.
8 max. (0.4V to 2.4V w/ TTL, 20% ~ 80% / HCMOS)
Option
2.4 min.
VDD-0.5 min.
23 ~ 50 max.
5.0 ±10%
UNITS
-
VDC
MHz
°C
°C
ppm
-
-
-
-
mA
ppm/Y
nS
-
VDC
VDC
%
mS
ps
High salary recruitment: automotive mold sales engineer
Requirements: 1. Develop new automotive customers, mainly foreign-funded and joint venture OEMs or OEMs, to improve the current situation of unsaturated orders and low utilization rate of the factory....
解优人才网 Talking about work
SIGe HBT and the development of high-speed circuits
The DC and AC characteristics, noise characteristics, structure, manufacturing process, process related parasitic effects, SIGe HBT on SOI substrate, and its applications in high-speed circuits, inclu...
JasonYoo Analog electronics
State Problems of State Machines in RISC CPU Design
When designing a CPU using FPGA, the current state of the state machine consists of 8 clock cycles. Each clock cycle must complete a fixed operation. The second clock and the sixth clock are no operat...
化羽成龙 FPGA/CPLD
A problem occurred when Cadence called the component
After placing a MOS tube in Cadence schematic editing, this error occurs. What is the reason? The library has been built....
eeleader FPGA/CPLD
Help: About the CAN bus of Freescale MC9S12XEP100
[color=#252525][size=14px]I need help, Freescale MC9S12XEP100 has two CAN bus interfaces. Are these two interfaces one input and one output? Or one high speed and one low speed? Or are they defined by...
焱阳高照 MCU
UCOS enters HardFault_Handler due to stack problem
Using UCOS, it is found that the newly created task enters HardFault_Handler after running. It is very likely that the allocated stack is too small (simply put, the memory allocated to the task is too...
weizhongc stm32/stm8

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 559  456  1557  1142  288  12  10  32  23  6 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号