EEWORLDEEWORLDEEWORLD

Part Number

Search

GHC259271PN6N

Description
GHC259271PN6N, CHIP
CategoryPassive components    capacitor   
File Size122KB,2 Pages
ManufacturerAVX
Environmental Compliance
Download Datasheet Parametric View All

GHC259271PN6N Overview

GHC259271PN6N, CHIP

GHC259271PN6N Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
package instructionCHIP,
Reach Compliance Codecompli
ECCN codeEAR99
capacitance0.00027 µF
Capacitor typeARRAY/NETWORK CAPACITOR
JESD-609 codee4
length1.65 mm
Manufacturer's serial numberGH
Installation featuresSURFACE MOUNT
negative tolerance
Network TypeISOLATED C NETWORK
Number of components1
Number of functions3
Number of terminals6
encapsulated codeCHIP
Package shapeRECTANGULAR PACKAGE
method of packingWAFFLE PACK
positive tolerance100%
Rated (DC) voltage (URdc)50 V
Maximum seat height0.203 mm
surface mountYES
Terminal surfaceGold (Au)
Terminal shapeONE SURFACE
width0.508 mm
Base Number Matches1
Microwave SLCs
Multi-Cap Arrays
GENERAL INFORMATION
AVX Multi-Cap Arrays are available with 2, 3, 4, 5 or 6
capacitors on one single layer capacitor substrate. Dual-
Caps are available in NP0, X7R, X7S (Z), Maxi and
Maxi+ dielectrics. Multi-Caps are available in dielectrics
Z, Maxi and Maxi+.
These arrays have advantages over single components
in the form of smaller overall size, reduced handling and
lower average unit costs. They are, therefore, a good
choice for broad-band bypass applications where circuit
board layouts can utilize these configurations.
The designs, shown along with the range of maximum
capacitance values, represent typical parts. Since most
applications require specific form factors, custom designs
on all multi-cap arrays are available to meet individual
customer requirements and are offered with quick turn
around. No charge samples are generally shipped within
two weeks of the design sign-off.
Both standard and custom designs are available with
borders for those applications where conductive epoxy
run up exposes the parts to the possibility of shorting.
Maximum capacitance per pad for bordered devices
will be necessarily somewhat lower than shown on the
adjacent page.
2 and 3 cap arrays can be designed with different
capacitance values per pad in circuit designs where
identical values pad-to-pad are, for one reason or another,
not altogether suitable.
Additionally, the dual-caps are available to match micro
strip widths as dictated by circuit considerations. When
mounted with the individual pads down, the need for
wire bonding is eliminated. The maximum capacitance
values indicated on the typical designs shown represent
capacitance per pad. Mounted with both pads down puts
two capacitors in series. The effective series capacitance
(C
Eff
), can be determined by 1/C
Eff
= 1/C1 + 1/C2.
Contact the factory or your local AVX representative.
DUAL-CAP
MULTI-CAP
T
G
W
G
W
L
T
L
12

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2049  2796  56  771  2320  42  57  2  16  47 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号