AS7C251MPFS18A-200BC datasheet, PDF

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AS7C251MPFS18A-200BC: DescriptionStandard SRAM, 1MX18, 7.5ns, CMOS, PBGA165, BGA-165; Categorystorage storage; File Size410KB，21 Pages; ManufacturerALSC [Alliance Semiconductor Corporation]

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AS7C251MPFS18A-200BC Overview

Standard SRAM, 1MX18, 7.5ns, CMOS, PBGA165, BGA-165

AS7C251MPFS18A-200BC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	ALSC [Alliance Semiconductor Corporation]
Parts packaging code	BGA
package instruction	TBGA,
Contacts	165
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	7.5 ns
Other features	FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	15 mm
memory density	18874368 bit
Memory IC Type	STANDARD SRAM
memory width	18
Number of functions	1
Number of terminals	165
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1MX18
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	13 mm

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December 2002

Advance Information

AS7C251MPFS18A

2.5V 1M x 18 pipelined burst synchronous SRAM

Features

•

Organization: 1,048,576 x18 bits

Fast clock speeds to 250MHz in LVTTL/LVCMOS

Fast clock to data access: 2.6/2.8/3/3.4 ns

Fast OE access time: 2.6/2.8/3/3.4 ns

Fully synchronous register-to-register operation

Single register flow-through mode

Single-cycle deselect

•

Asynchronous output enable control

Available 100-pin TQFP and 165-ball BGA packages

Byte write enables

Multiple chip enables for easy expansion

2.5V core power supply

NTD™ pipelined architecture available (AS7C251MNTD18A,

AS7C25512NTD32A/ AS7C25512NTD36A)

Logic block diagram

LBO

CLK

ADV

ADSC

ADSP

A[19:0]

CLK

CLR

Burst logic

CLK

18 20

Address

[

Memory

array

GWE

BWE

CE0

CE1

CE2

DQb

Byte Write

registers

Byte Write

registers

CLK

DQa

Enable

CLK

Output

registers

CLK

Input

registers

CLK

Power

down

Enable

delay

CLK

FT DQ[a,b]

Selection guide

Minimum cycle time

Maximum clock frequency

Maximum pipelined clock access time

Maximum operating current

Maximum standby current

Maximum CMOS standby current (DC)

-250

250

2.6

425

110

-225

4.4

225

2.8

400

110

-200

200

3.0

370

110

-166

166

3.4

340

Units

MHz

12/2/02, v. 0.9.2 Advance Info

Alliance Semiconductor

1 of 21

AS7C251MPFS18A

Functional description

The AS7C251MPFS18A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device organized as

1,048,576 words X 18 bits and incorporates a two-stage register-register pipeline for highest frequency on any given technology.

Fast cycle times of 4/4.4/5/6 ns with clock access times (t

) of 2.6/2.8/3/3.4 ns enable 250, 225, 200, and 166 MHz bus frequencies.

Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe

(ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.

Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register

when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data

accessed by the current address registered in the address registers by the positive edge of CLK is carried to the data-out registers and driven on

the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but it is sampled on all

subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled low and both address strobes

are high. Burst mode is selectable with the LBO input. With LBO unconnected or driven high, burst operations use an interleaved count

sequence. With LBO driven low, the device uses a linear count sequence.

Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all

18 bits regardless of the state of individual BW[a,b] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting

BWE and the appropriate individual byte BWn signals.

BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled when

BWn is sampled low, regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented internally

to the next burst address if BWn and ADV are sampled low.

Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.

• ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.

• WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).

•

Master chip enable

CE0 blocks ADSP, but not ADSC.

The AS7C251MPFS18A family operates from a core 2.5V power supply. These devices are available in a 100-pin TQFP and 165-ball BGA.

TQFP and BGA capacitance

Parameter

Input capacitance

I/O capacitance

Symbol

I/O

Signals

Address and control pins

I/O pins

Test conditions

= 0V

= V

OUT

Max

Unit

12/2/02, v. 0.9.2 Advance Info

Alliance Semiconductor

3 of 21

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